std_div.v

来自「自动售货机的程序」· Verilog 代码 · 共 45 行

module std_div(clk_in,clk_out);

input clk_in;
output clk_out;

reg[div_width-1:0] counter;
reg full;
reg clk_temp;

parameter diver=12000;
parameter div_width=25;

assign clk_out=clk_temp;

always@(posedge clk_in)
begin
	if(counter==diver/2-1)
	begin
		counter<=0;
		full<=1'b1;
	end
	else
	begin
		counter<=counter+1'b1;
		full<=1'b0;
	end
end

always@(posedge clk_in)
begin
	if(full==1)
		clk_temp<=~clk_temp;
	else
		clk_temp<=clk_temp;
end

endmodule