seller.tan.rpt

自动售货机的程序

; N/A                                     ; 230.63 MHz ( period = 4.336 ns )                    ; Reset_Delay:inst2|Cont[11] ; Reset_Delay:inst2|Cont[14] ; clk_in     ; clk_in   ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 230.63 MHz ( period = 4.336 ns )                    ; Reset_Delay:inst2|Cont[11] ; Reset_Delay:inst2|Cont[13] ; clk_in     ; clk_in   ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 231.96 MHz ( period = 4.311 ns )                    ; debounce:inst3|dout3[0]    ; seller:inst|in_wujiao_reg  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.144 ns                ;
; N/A                                     ; 232.07 MHz ( period = 4.309 ns )                    ; debounce:inst3|dout2[0]    ; seller:inst|in_wujiao_reg  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.142 ns                ;
; N/A                                     ; 234.14 MHz ( period = 4.271 ns )                    ; std_div:inst1|counter[3]   ; std_div:inst1|counter[13]  ; clk_in     ; clk_in   ; None                        ; None                      ; 4.032 ns                ;
; N/A                                     ; 234.47 MHz ( period = 4.265 ns )                    ; debounce:inst3|dout1[0]    ; seller:inst|in_wujiao_reg  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.098 ns                ;
; N/A                                     ; 235.96 MHz ( period = 4.238 ns )                    ; Reset_Delay:inst2|Cont[14] ; Reset_Delay:inst2|Cont[9]  ; clk_in     ; clk_in   ; None                        ; None                      ; 4.008 ns                ;
; N/A                                     ; 235.96 MHz ( period = 4.238 ns )                    ; Reset_Delay:inst2|Cont[14] ; Reset_Delay:inst2|Cont[11] ; clk_in     ; clk_in   ; None                        ; None                      ; 4.008 ns                ;
; N/A                                     ; 235.96 MHz ( period = 4.238 ns )                    ; Reset_Delay:inst2|Cont[14] ; Reset_Delay:inst2|Cont[10] ; clk_in     ; clk_in   ; None                        ; None                      ; 4.008 ns                ;
; N/A                                     ; 235.96 MHz ( period = 4.238 ns )                    ; Reset_Delay:inst2|Cont[14] ; Reset_Delay:inst2|Cont[8]  ; clk_in     ; clk_in   ; None                        ; None                      ; 4.008 ns                ;
; N/A                                     ; 235.96 MHz ( period = 4.238 ns )                    ; Reset_Delay:inst2|Cont[14] ; Reset_Delay:inst2|Cont[4]  ; clk_in     ; clk_in   ; None                        ; None                      ; 4.008 ns                ;
; N/A                                     ; 235.96 MHz ( period = 4.238 ns )                    ; Reset_Delay:inst2|Cont[14] ; Reset_Delay:inst2|Cont[7]  ; clk_in     ; clk_in   ; None                        ; None                      ; 4.008 ns                ;
; N/A                                     ; 235.96 MHz ( period = 4.238 ns )                    ; Reset_Delay:inst2|Cont[14] ; Reset_Delay:inst2|Cont[6]  ; clk_in     ; clk_in   ; None                        ; None                      ; 4.008 ns                ;
; N/A                                     ; 235.96 MHz ( period = 4.238 ns )                    ; Reset_Delay:inst2|Cont[14] ; Reset_Delay:inst2|Cont[5]  ; clk_in     ; clk_in   ; None                        ; None                      ; 4.008 ns                ;
; N/A                                     ; 235.96 MHz ( period = 4.238 ns )                    ; Reset_Delay:inst2|Cont[14] ; Reset_Delay:inst2|Cont[3]  ; clk_in     ; clk_in   ; None                        ; None                      ; 4.008 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                            ;                            ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+----------------------------+----------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------------------+
; tsu                                                                                ;
+-------+--------------+------------+-----------+-------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From      ; To                      ; To Clock ;
+-------+--------------+------------+-----------+-------------------------+----------+
; N/A   ; None         ; 1.429 ns   ; key_in[1] ; debounce:inst3|dout1[1] ; clk_in   ;
; N/A   ; None         ; 1.086 ns   ; key_in[0] ; debounce:inst3|dout1[0] ; clk_in   ;
+-------+--------------+------------+-----------+-------------------------+----------+


+-----------------------------------------------------------------------------------+
; tco                                                                               ;
+-------+--------------+------------+--------------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From                     ; To    ; From Clock ;
+-------+--------------+------------+--------------------------+-------+------------+
; N/A   ; None         ; 7.822 ns   ; seller:inst|sell_succeed ; sell  ; clk_in     ;
; N/A   ; None         ; 7.753 ns   ; seller:inst|get_change   ; get   ; clk_in     ;
; N/A   ; None         ; 7.428 ns   ; seller:inst|sell_succeed ; fetch ; clk_in     ;
+-------+--------------+------------+--------------------------+-------+------------+


+------------------------------------------------------------------------------------------+
; th                                                                                       ;
+---------------+-------------+-----------+-----------+-------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To                      ; To Clock ;
+---------------+-------------+-----------+-----------+-------------------------+----------+
; N/A           ; None        ; -0.838 ns ; key_in[0] ; debounce:inst3|dout1[0] ; clk_in   ;
; N/A           ; None        ; -1.181 ns ; key_in[1] ; debounce:inst3|dout1[1] ; clk_in   ;
+---------------+-------------+-----------+-----------+-------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Nov 23 14:56:51 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seller -c seller --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_in" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "std_div:inst1|clk_temp" as buffer
Info: Clock "clk_in" has Internal fmax of 175.13 MHz between source register "debounce:inst3|dout2[1]" and destination register "seller:inst|PS.idle" (period= 5.71 ns)
    Info: + Longest register to register delay is 2.542 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X43_Y14_N3; Fanout = 3; REG Node = 'debounce:inst3|dout2[1]'
        Info: 2: + IC(0.378 ns) + CELL(0.521 ns) = 0.899 ns; Loc. = LCCOMB_X43_Y14_N12; Fanout = 6; COMB Node = 'seller:inst|in_yikuai_reg~68'
        Info: 3: + IC(0.532 ns) + CELL(0.322 ns) = 1.753 ns; Loc. = LCCOMB_X43_Y14_N4; Fanout = 1; COMB Node = 'se