gzip.golden.beforelogtm

testing the command s with the given input space

  Regs                       0          0          0
  RegRet                     0          0          0
   STATIC           952      96.12%

*** # of outstanding misses
Hash Table entries: 0
*** Interarrival times
Hash Table entries: 0
*** Dependent ops instrs
Hash Table entries: 0
*** Effective
Hash Table entries: 0
*** Not Effective
Hash Table entries: 0
*** inter cluster
Hash Table entries: 0
*** Pipeline statistics:
  cycle of decode stalls:                                     0
  insts of decode of stall:                                   0
  cycle of schedule stalls:                               45044
  insts of schedule of stall:                           2536796
  count early store bypasses:                                 0
  total number of asi store squashes:                         0
  count failed retirements:                                   0
  count functional retirements:                               0
  count of I/O loads/stores:                                  0
  count done/retry squashes:                                  0
  number of instructions read from trace:                     0
  total number of instructions committed:                100003
  total number of times squash is called:                  1124
  total number of instructions squashing at commit:           0
  total number of instructions committing successful     100003
  total number of instructions committing unsuccessf          0
  total number of unimplemented instructions committ          0
  total number of instructions fetched:                  170024
  total number of mini-itlb misses:                           0
  total number of instructions decoded:                  162072
  total number of instructions executed:                 121757
  total number of loads executed:                         14221
  total number of stores executed:                        15181
  total number of atomics executed:                           0
  total number of prefetches executed:                        0
  total number of control insts executed:                 27718
  total number of loads retired:                          12262
  total number of stores retired:                         12263
  total number of atomics retired:                            0
  total number of prefetches retired:                         0
  total number of control instrs committed:               25476
  loads with valid data at executed:                      14133
  loads with invalid data at execute:                         0
  total number of spill traps:                                0
  total number of fill traps:                                 0
  number fetches executed which miss in icache               12
  number misses fetches that hit in mshr                      0
  number loads executed which miss in dcache               6209
  retiring data cache misses                               2418
  retiring L2 misses                                          0
  retiring MSHR hits                                          0
  number of times ruby is not ready                           0
  number of loads satisfied by store queue:                   0
  number of stores scheduled before value:                  561
  number of loads waiting for early store resolution          0
  number of atomics scheduled before value:                   0
  number of stale data speculations                           0
  number of successful stale predictions:                     0
  stale prediction size =                               1          0
  stale prediction size =                               2          0
  stale prediction size =                               4          0
  stale prediction size =                               8          0
  stale prediction size =                              16          0
  stale prediction size =                              32          0
  stale prediction size =                              64          0

  L2.unified total number of reads:                            :       58
  L2.unified total number of read hits:                        :        0
  L2.unified total number of read misses:                      :       58
  L2.unified total number of writes:                           :      330
  L2.unified total number of write hits:                       :        0
  L2.unified total number of write misses:                     :      330
  L2.unified number of write prefetches:                       :        0
  L2.unified total number of replacements:                     :        0
  L2.unified total number of writebacks:                       :        0
  L2.unified demand miss per 1000 retired instructions:        :     3.88

  L2.mshr histogram of misses outanding
    Name     [out]  number    pct
    L2.mshr  [  0]    39247 52.75%
    L2.mshr  [  1]    34985 47.02%
    L2.mshr  [  2]      166  0.22%
    L2.mshr [tot]    74398
  L2.mshr Average parallel misses                           :  1.00472
  L2.mshr total number of primary misses                    :      388
  L2.mshr total number of secondary misses                  :        0
  L2.mshr number of prefetches that hit in prefetch buffer  :        0
  L2.mshr number of stream buffer prefetches launched       :        0
  L2.mshr number of inflight prefetched upgraded to demands :        0
  L2.mshr number of misses serviced from prefetch buffer    :        0
  L2.mshr number of misses serviced from victim buffer      :        0

  L1.data total number of reads:                            :    14213
  L1.data total number of read hits:                        :    11068
  L1.data total number of read misses:                      :     3145
  L1.data total number of writes:                           :    15073
  L1.data total number of write hits:                       :    12009
  L1.data total number of write misses:                     :     3064
  L1.data number of write prefetches:                       :       71
  L1.data total number of replacements:                     :        0
  L1.data total number of writebacks:                       :        0
  L1.data demand miss per 1000 retired instructions:        :    62.09

  DL1.mshr histogram of misses outanding
    Name     [out]  number    pct
    DL1.mshr [  0]    36757 49.41%
    DL1.mshr [  1]    37641 50.59%
    DL1.mshr [tot]    74398
  DL1.mshr Average parallel misses                           :  1.00000
  DL1.mshr total number of primary misses                    :      384
  DL1.mshr total number of secondary misses                  :     5896
  DL1.mshr number of prefetches that hit in prefetch buffer  :        0
  DL1.mshr number of stream buffer prefetches launched       :        0
  DL1.mshr number of inflight prefetched upgraded to demands :        0
  DL1.mshr number of misses serviced from prefetch buffer    :        0
  DL1.mshr number of misses serviced from victim buffer      :        0

  L1.inst total number of reads:                            :     3898
  L1.inst total number of read hits:                        :     3886
  L1.inst total number of read misses:                      :       12
  L1.inst total number of writes:                           :        0
  L1.inst total number of write hits:                       :        0
  L1.inst total number of write misses:                     :        0
  L1.inst number of write prefetches:                       :        0
  L1.inst total number of replacements:                     :        0
  L1.inst total number of writebacks:                       :        0
  L1.inst demand miss per 1000 retired instructions:        :     0.12

  IL1.mshr histogram of misses outanding
    Name     [out]  number    pct
    IL1.mshr [  0]    74090 99.59%
    IL1.mshr [  1]      224  0.30%
    IL1.mshr [  2]       84  0.11%
    IL1.mshr [tot]    74398
  IL1.mshr Average parallel misses                           :  1.27273
  IL1.mshr total number of primary misses                    :        4
  IL1.mshr total number of secondary misses                  :        8
  IL1.mshr number of prefetches that hit in prefetch buffer  :        0
  IL1.mshr number of stream buffer prefetches launched       :        0
  IL1.mshr number of inflight prefetched upgraded to demands :        0
  IL1.mshr number of misses serviced from prefetch buffer    :        0
  IL1.mshr number of misses serviced from victim buffer      :        0
Instruction Page Map Statistics:
   Total number of pages     : 0
   Total number of collisions: 0
*** Runtime statistics:
  Total number of instructions                           100003
  Total number of cycles                                  74398
  number of continue calls                                    0
  Instruction per cycle:                             1.34416
  Total Elapsed Time:                                3 sec 0 usec
  Total Retirement Time:                             0 sec 0 usec
  Approximate cycle per sec:                         24171.1
  Approximate instructions per sec:                  32489.8
  This processor's Simics overhead (retire/elapsed):   0.00%
removing memory hierarchy
closing file /p/multifacet/projects/regress/opal_traces/gzip/gzip-trace
closing memop trace file /p/multifacet/projects/regress/opal_traces/gzip/mem-gzip-trace
high fidelity architecture code uninstalled.