add1.tan.qmsg

8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器

{ "Info" "ITDB_TSU_RESULT" "r\[7\] sign1 clk 27.400 ns register " "Info: tsu for register \"r\[7\]\" (data pin = \"sign1\", clock pin = \"clk\") is 27.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "28.600 ns + Longest pin register " "Info: + Longest pin to register delay is 28.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns sign1 1 PIN PIN_95 17 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_95; Fanout = 17; PIN Node = 'sign1'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "" { sign1 } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.400 ns) + CELL(1.900 ns) 10.400 ns co\[0\]~662 2 COMB LC2_B35 2 " "Info: 2: + IC(5.400 ns) + CELL(1.900 ns) = 10.400 ns; Loc. = LC2_B35; Fanout = 2; COMB Node = 'co\[0\]~662'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "7.300 ns" { sign1 co[0]~662 } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(2.000 ns) 14.300 ns co\[1\]~663 3 COMB LC5_B47 2 " "Info: 3: + IC(1.900 ns) + CELL(2.000 ns) = 14.300 ns; Loc. = LC5_B47; Fanout = 2; COMB Node = 'co\[1\]~663'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "3.900 ns" { co[0]~662 co[1]~663 } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 16.500 ns co\[2\]~664 4 COMB LC6_B47 2 " "Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 16.500 ns; Loc. = LC6_B47; Fanout = 2; COMB Node = 'co\[2\]~664'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "2.200 ns" { co[1]~663 co[2]~664 } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 18.700 ns co\[3\]~665 5 COMB LC3_B47 2 " "Info: 5: + IC(0.200 ns) + CELL(2.000 ns) = 18.700 ns; Loc. = LC3_B47; Fanout = 2; COMB Node = 'co\[3\]~665'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "2.200 ns" { co[2]~664 co[3]~665 } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(2.000 ns) 22.700 ns co\[4\]~666 6 COMB LC1_B34 2 " "Info: 6: + IC(2.000 ns) + CELL(2.000 ns) = 22.700 ns; Loc. = LC1_B34; Fanout = 2; COMB Node = 'co\[4\]~666'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "4.000 ns" { co[3]~665 co[4]~666 } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 24.900 ns co\[5\]~667 7 COMB LC2_B34 2 " "Info: 7: + IC(0.200 ns) + CELL(2.000 ns) = 24.900 ns; Loc. = LC2_B34; Fanout = 2; COMB Node = 'co\[5\]~667'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "2.200 ns" { co[4]~666 co[5]~667 } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 27.100 ns co\[6\]~668 8 COMB LC6_B34 3 " "Info: 8: + IC(0.200 ns) + CELL(2.000 ns) = 27.100 ns; Loc. = LC6_B34; Fanout = 3; COMB Node = 'co\[6\]~668'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "2.200 ns" { co[5]~667 co[6]~668 } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.300 ns) 28.600 ns r\[7\] 9 REG LC7_B34 4 " "Info: 9: + IC(0.200 ns) + CELL(1.300 ns) = 28.600 ns; Loc. = LC7_B34; Fanout = 4; REG Node = 'r\[7\]'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.500 ns" { co[6]~668 r[7] } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.300 ns 63.99 % " "Info: Total cell delay = 18.300 ns ( 63.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.300 ns 36.01 % " "Info: Total interconnect delay = 10.300 ns ( 36.01 % )" {  } {  } 0}  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "28.600 ns" { sign1 co[0]~662 co[1]~663 co[2]~664 co[3]~665 co[4]~666 co[5]~667 co[6]~668 r[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "28.600 ns" { sign1 sign1~out co[0]~662 co[1]~663 co[2]~664 co[3]~665 co[4]~666 co[5]~667 co[6]~668 r[7] } { 0.000ns 0.000ns 5.400ns 1.900ns 0.200ns 0.200ns 2.000ns 0.200ns 0.200ns 0.200ns } { 0.000ns 3.100ns 1.900ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 1.300ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 10 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 10; CLK Node = 'clk'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "" { clk } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns r\[7\] 2 REG LC7_B34 4 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_B34; Fanout = 4; REG Node = 'r\[7\]'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.400 ns" { clk r[7] } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.900 ns" { clk r[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out r[7] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "28.600 ns" { sign1 co[0]~662 co[1]~663 co[2]~664 co[3]~665 co[4]~666 co[5]~667 co[6]~668 r[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "28.600 ns" { sign1 sign1~out co[0]~662 co[1]~663 co[2]~664 co[3]~665 co[4]~666 co[5]~667 co[6]~668 r[7] } { 0.000ns 0.000ns 5.400ns 1.900ns 0.200ns 0.200ns 2.000ns 0.200ns 0.200ns 0.200ns } { 0.000ns 3.100ns 1.900ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 1.300ns } } } { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.900 ns" { clk r[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out r[7] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk z r\[4\] 19.800 ns register " "Info: tco from clock \"clk\" to destination pin \"z\" through register \"r\[4\]\" is 19.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 10 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 10; CLK Node = 'clk'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "" { clk } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns r\[4\] 2 REG LC4_B40 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_B40; Fanout = 2; REG Node = 'r\[4\]'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.400 ns" { clk r[4] } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.900 ns" { clk r[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out r[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.800 ns + Longest register pin " "Info: + Longest register to pin delay is 16.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns r\[4\] 1 REG LC4_B40 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B40; Fanout = 2; REG Node = 'r\[4\]'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "" { r[4] } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.500 ns) 3.300 ns reduce_nor~52 2 COMB LC6_B35 1 " "Info: 2: + IC(1.800 ns) + CELL(1.500 ns) = 3.300 ns; Loc. = LC6_B35; Fanout = 1; COMB Node = 'reduce_nor~52'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "3.300 ns" { r[4] reduce_nor~52 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 5.200 ns reduce_nor~49 3 COMB LC7_B35 1 " "Info: 3: + IC(0.000 ns) + CELL(1.900 ns) = 5.200 ns; Loc. = LC7_B35; Fanout = 1; COMB Node = 'reduce_nor~49'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.900 ns" { reduce_nor~52 reduce_nor~49 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 7.100 ns z~0 4 COMB LC3_B35 1 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.100 ns; Loc. = LC3_B35; Fanout = 1; COMB Node = 'z~0'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.900 ns" { reduce_nor~49 z~0 } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(8.500 ns) 16.800 ns z 5 PIN PIN_191 0 " "Info: 5: + IC(1.200 ns) + CELL(8.500 ns) = 16.800 ns; Loc. = PIN_191; Fanout = 0; PIN Node = 'z'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "9.700 ns" { z~0 z } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.600 ns 80.95 % " "Info: Total cell delay = 13.600 ns ( 80.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns 19.05 % " "Info: Total interconnect delay = 3.200 ns ( 19.05 % )" {  } {  } 0}  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "16.800 ns" { r[4] reduce_nor~52 reduce_nor~49 z~0 z } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.800 ns" { r[4] reduce_nor~52 reduce_nor~49 z~0 z } { 0.000ns 1.800ns 0.000ns 0.200ns 1.200ns } { 0.000ns 1.500ns 1.900ns 1.700ns 8.500ns } } }  } 0}  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.900 ns" { clk r[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out r[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "16.800 ns" { r[4] reduce_nor~52 reduce_nor~49 z~0 z } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.800 ns" { r[4] reduce_nor~52 reduce_nor~49 z~0 z } { 0.000ns 1.800ns 0.000ns 0.200ns 1.200ns } { 0.000ns 1.500ns 1.900ns 1.700ns 8.500ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "sign1 v 22.300 ns Longest " "Info: Longest tpd from source pin \"sign1\" to destination pin \"v\" is 22.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns sign1 1 PIN PIN_95 17 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_95; Fanout = 17; PIN Node = 'sign1'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "" { sign1 } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.500 ns) + CELL(1.900 ns) 10.500 ns b_data\[7\]~44 2 COMB LC2_B37 1 " "Info: 2: + IC(5.500 ns) + CELL(1.900 ns) = 10.500 ns; Loc. = LC2_B37; Fanout = 1; COMB Node = 'b_data\[7\]~44'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "7.400 ns" { sign1 b_data[7]~44 } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 12.600 ns process1~3 3 COMB LC1_B37 1 " "Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 12.600 ns; Loc. = LC1_B37; Fanout = 1; COMB Node = 'process1~3'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "2.100 ns" { b_data[7]~44 process1~3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(8.500 ns) 22.300 ns v 4 PIN PIN_192 0 " "Info: 4: + IC(1.200 ns) + CELL(8.500 ns) = 22.300 ns; Loc. = PIN_192; Fanout = 0; PIN Node = 'v'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "9.700 ns" { process1~3 v } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.400 ns 69.06 % " "Info: Total cell delay = 15.400 ns ( 69.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns 30.94 % " "Info: Total interconnect delay = 6.900 ns ( 30.94 % )" {  } {  } 0}  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "22.300 ns" { sign1 b_data[7]~44 process1~3 v } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "22.300 ns" { sign1 sign1~out b_data[7]~44 process1~3 v } { 0.000ns 0.000ns 5.500ns 0.200ns 1.200ns } { 0.000ns 3.100ns 1.900ns 1.900ns 8.500ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "r\[6\] a\[6\] clk -5.100 ns register " "Info: th for register \"r\[6\]\" (data pin = \"a\[6\]\", clock pin = \"clk\") is -5.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 10 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 10; CLK Node = 'clk'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "" { clk } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns r\[6\] 2 REG LC3_B34 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_B34; Fanout = 2; REG Node = 'r\[6\]'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.400 ns" { clk r[6] } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.900 ns" { clk r[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out r[6] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns a\[6\] 1 PIN PIN_74 2 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_74; Fanout = 2; PIN Node = 'a\[6\]'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "" { a[6] } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(1.000 ns) 7.900 ns r\[6\] 2 REG LC3_B34 2 " "Info: 2: + IC(3.800 ns) + CELL(1.000 ns) = 7.900 ns; Loc. = LC3_B34; Fanout = 2; REG Node = 'r\[6\]'" {  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "4.800 ns" { a[6] r[6] } "NODE_NAME" } "" } } { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.100 ns 51.90 % " "Info: Total cell delay = 4.100 ns ( 51.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.800 ns 48.10 % " "Info: Total interconnect delay = 3.800 ns ( 48.10 % )" {  } {  } 0}  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "7.900 ns" { a[6] r[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.900 ns" { a[6] a[6]~out r[6] } { 0.000ns 0.000ns 3.800ns } { 0.000ns 3.100ns 1.000ns } } }  } 0}  } { { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "1.900 ns" { clk r[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out r[6] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "C:/altera/quartus50/333/db/add1_cmp.qrpt" "" { Report "C:/altera/quartus50/333/db/add1_cmp.qrpt" Compiler "add1" "UNKNOWN" "V1" "C:/altera/quartus50/333/db/add1.quartus_db" { Floorplan "C:/altera/quartus50/333/" "" "7.900 ns" { a[6] r[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.900 ns" { a[6] a[6]~out r[6] } { 0.000ns 0.000ns 3.800ns } { 0.000ns 3.100ns 1.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 22 13:57:56 2006 " "Info: Processing ended: Wed Feb 22 13:57:56 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}