add1.map.eqn

8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--r[0] is r[0]
--operation mode is normal

r[0]_lut_out = ci $ b[0] $ a[0];
r[0] = DFFEA(r[0]_lut_out, clk, , , , , );

--A1L54Q is r[0]~56
--operation mode is normal

A1L54Q = r[0];


--r[1] is r[1]
--operation mode is normal

r[1]_lut_out = A1L62 $ sign1 $ b[1] $ a[1];
r[1] = DFFEA(r[1]_lut_out, clk, , , , , );

--A1L74Q is r[1]~57
--operation mode is normal

A1L74Q = r[1];


--r[2] is r[2]
--operation mode is normal

r[2]_lut_out = A1L82 $ sign1 $ b[2] $ a[2];
r[2] = DFFEA(r[2]_lut_out, clk, , , , , );

--A1L94Q is r[2]~58
--operation mode is normal

A1L94Q = r[2];


--r[3] is r[3]
--operation mode is normal

r[3]_lut_out = A1L03 $ sign1 $ b[3] $ a[3];
r[3] = DFFEA(r[3]_lut_out, clk, , , , , );

--A1L15Q is r[3]~59
--operation mode is normal

A1L15Q = r[3];


--r[4] is r[4]
--operation mode is normal

r[4]_lut_out = A1L23 $ sign1 $ b[4] $ a[4];
r[4] = DFFEA(r[4]_lut_out, clk, , , , , );

--A1L35Q is r[4]~60
--operation mode is normal

A1L35Q = r[4];


--r[5] is r[5]
--operation mode is normal

r[5]_lut_out = A1L43 $ sign1 $ b[5] $ a[5];
r[5] = DFFEA(r[5]_lut_out, clk, , , , , );

--A1L55Q is r[5]~61
--operation mode is normal

A1L55Q = r[5];


--r[6] is r[6]
--operation mode is normal

r[6]_lut_out = A1L63 $ sign1 $ b[6] $ a[6];
r[6] = DFFEA(r[6]_lut_out, clk, , , , , );

--A1L75Q is r[6]~62
--operation mode is normal

A1L75Q = r[6];


--r[7] is r[7]
--operation mode is normal

r[7]_lut_out = a[7] $ A1L83 $ sign1 $ b[7];
r[7] = DFFEA(r[7]_lut_out, clk, , , , , );

--A1L95Q is r[7]~63
--operation mode is normal

A1L95Q = r[7];


--carryout is carryout
--operation mode is normal

carryout_lut_out = a[7] & (A1L83 # sign1 $ b[7]) # !a[7] & A1L83 & (sign1 $ b[7]);
carryout = DFFEA(carryout_lut_out, clk, , , , , );

--A1L32Q is carryout~0
--operation mode is normal

A1L32Q = carryout;


--A1L91 is b_data[7]~44
--operation mode is normal

A1L91 = sign1 $ b[7];

--A1L02 is b_data[7]~45
--operation mode is normal

A1L02 = sign1 $ b[7];


--A1L14 is process1~3
--operation mode is normal

A1L14 = sign & (a[7] & A1L91 & !r[7] # !a[7] & !A1L91 & r[7]);

--A1L24 is process1~80
--operation mode is normal

A1L24 = sign & (a[7] & A1L91 & !r[7] # !a[7] & !A1L91 & r[7]);


--A1L86 is s~9
--operation mode is normal

A1L86 = r[7] & sign;

--A1L96 is s~10
--operation mode is normal

A1L96 = r[7] & sign;


--A1L62 is co[0]~662
--operation mode is normal

A1L62 = b[0] & (ci # a[0]) # !b[0] & (sign1 # ci & a[0]);

--A1L72 is co[0]~670
--operation mode is normal

A1L72 = b[0] & (ci # a[0]) # !b[0] & (sign1 # ci & a[0]);


--A1L82 is co[1]~663
--operation mode is normal

A1L82 = a[1] & (A1L62 # sign1 $ b[1]) # !a[1] & A1L62 & (sign1 $ b[1]);

--A1L92 is co[1]~671
--operation mode is normal

A1L92 = a[1] & (A1L62 # sign1 $ b[1]) # !a[1] & A1L62 & (sign1 $ b[1]);


--A1L03 is co[2]~664
--operation mode is normal

A1L03 = a[2] & (A1L82 # sign1 $ b[2]) # !a[2] & A1L82 & (sign1 $ b[2]);

--A1L13 is co[2]~672
--operation mode is normal

A1L13 = a[2] & (A1L82 # sign1 $ b[2]) # !a[2] & A1L82 & (sign1 $ b[2]);


--A1L23 is co[3]~665
--operation mode is normal

A1L23 = a[3] & (A1L03 # sign1 $ b[3]) # !a[3] & A1L03 & (sign1 $ b[3]);

--A1L33 is co[3]~673
--operation mode is normal

A1L33 = a[3] & (A1L03 # sign1 $ b[3]) # !a[3] & A1L03 & (sign1 $ b[3]);


--A1L43 is co[4]~666
--operation mode is normal

A1L43 = a[4] & (A1L23 # sign1 $ b[4]) # !a[4] & A1L23 & (sign1 $ b[4]);

--A1L53 is co[4]~674
--operation mode is normal

A1L53 = a[4] & (A1L23 # sign1 $ b[4]) # !a[4] & A1L23 & (sign1 $ b[4]);


--A1L63 is co[5]~667
--operation mode is normal

A1L63 = a[5] & (A1L43 # sign1 $ b[5]) # !a[5] & A1L43 & (sign1 $ b[5]);

--A1L73 is co[5]~675
--operation mode is normal

A1L73 = a[5] & (A1L43 # sign1 $ b[5]) # !a[5] & A1L43 & (sign1 $ b[5]);


--A1L83 is co[6]~668
--operation mode is normal

A1L83 = a[6] & (A1L63 # sign1 $ b[6]) # !a[6] & A1L63 & (sign1 $ b[6]);

--A1L93 is co[6]~676
--operation mode is normal

A1L93 = a[6] & (A1L63 # sign1 $ b[6]) # !a[6] & A1L63 & (sign1 $ b[6]);


--A1L06 is reduce_nor~47
--operation mode is normal

A1L06 = !r[4] & !r[5] & !r[6] & !r[7];

--A1L26 is reduce_nor~51
--operation mode is normal

A1L26 = !r[4] & !r[5] & !r[6] & !r[7];

--A1L36 is reduce_nor~52
--operation mode is normal

A1L36 = !r[4] & !r[5] & !r[6] & !r[7];


--A1L16 is reduce_nor~49
--operation mode is normal

A1L16 = (!r[0] & !r[1] & !r[2] & !r[3]) & CASCADE(A1L36);

--A1L46 is reduce_nor~53
--operation mode is normal

A1L46 = (!r[0] & !r[1] & !r[2] & !r[3]) & CASCADE(A1L36);


--sign is sign
--operation mode is input

sign = INPUT();


--a[7] is a[7]
--operation mode is input

a[7] = INPUT();


--sign1 is sign1
--operation mode is input

sign1 = INPUT();


--b[7] is b[7]
--operation mode is input

b[7] = INPUT();


--ci is ci
--operation mode is input

ci = INPUT();


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--a[0] is a[0]
--operation mode is input

a[0] = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--b[2] is b[2]
--operation mode is input

b[2] = INPUT();


--a[2] is a[2]
--operation mode is input

a[2] = INPUT();


--b[3] is b[3]
--operation mode is input

b[3] = INPUT();


--a[3] is a[3]
--operation mode is input

a[3] = INPUT();


--b[4] is b[4]
--operation mode is input

b[4] = INPUT();


--a[4] is a[4]
--operation mode is input

a[4] = INPUT();


--b[5] is b[5]
--operation mode is input

b[5] = INPUT();


--a[5] is a[5]
--operation mode is input

a[5] = INPUT();


--b[6] is b[6]
--operation mode is input

b[6] = INPUT();


--a[6] is a[6]
--operation mode is input

a[6] = INPUT();


--y_out[0] is y_out[0]
--operation mode is output

y_out[0] = OUTPUT(r[0]);


--y_out[1] is y_out[1]
--operation mode is output

y_out[1] = OUTPUT(r[1]);


--y_out[2] is y_out[2]
--operation mode is output

y_out[2] = OUTPUT(r[2]);


--y_out[3] is y_out[3]
--operation mode is output

y_out[3] = OUTPUT(r[3]);


--y_out[4] is y_out[4]
--operation mode is output

y_out[4] = OUTPUT(r[4]);


--y_out[5] is y_out[5]
--operation mode is output

y_out[5] = OUTPUT(r[5]);


--y_out[6] is y_out[6]
--operation mode is output

y_out[6] = OUTPUT(r[6]);


--y_out[7] is y_out[7]
--operation mode is output

y_out[7] = OUTPUT(r[7]);


--co_out is co_out
--operation mode is output

co_out = OUTPUT(carryout);


--c is c
--operation mode is output

c = OUTPUT(carryout);


--z is z
--operation mode is output

z = OUTPUT(A1L16);


--v is v
--operation mode is output

v = OUTPUT(A1L14);


--s is s
--operation mode is output

s = OUTPUT(A1L86);