📄 add1.tan.rpt
字号:
; N/A ; None ; -9.900 ns ; a[3] ; r[4] ; clk ;
; N/A ; None ; -9.900 ns ; b[0] ; r[1] ; clk ;
; N/A ; None ; -10.000 ns ; a[5] ; r[7] ; clk ;
; N/A ; None ; -10.000 ns ; a[5] ; carryout ; clk ;
; N/A ; None ; -10.000 ns ; a[5] ; carryout~1 ; clk ;
; N/A ; None ; -10.100 ns ; a[0] ; r[1] ; clk ;
; N/A ; None ; -10.200 ns ; b[5] ; r[7] ; clk ;
; N/A ; None ; -10.200 ns ; b[5] ; carryout ; clk ;
; N/A ; None ; -10.200 ns ; b[5] ; carryout~1 ; clk ;
; N/A ; None ; -10.400 ns ; b[1] ; r[3] ; clk ;
; N/A ; None ; -10.500 ns ; b[4] ; r[6] ; clk ;
; N/A ; None ; -10.700 ns ; ci ; r[1] ; clk ;
; N/A ; None ; -10.900 ns ; a[4] ; r[6] ; clk ;
; N/A ; None ; -11.000 ns ; a[1] ; r[3] ; clk ;
; N/A ; None ; -12.100 ns ; b[3] ; r[5] ; clk ;
; N/A ; None ; -12.100 ns ; b[2] ; r[4] ; clk ;
; N/A ; None ; -12.100 ns ; b[0] ; r[2] ; clk ;
; N/A ; None ; -12.200 ns ; a[3] ; r[5] ; clk ;
; N/A ; None ; -12.300 ns ; a[0] ; r[2] ; clk ;
; N/A ; None ; -12.500 ns ; b[4] ; r[7] ; clk ;
; N/A ; None ; -12.500 ns ; b[4] ; carryout ; clk ;
; N/A ; None ; -12.500 ns ; b[4] ; carryout~1 ; clk ;
; N/A ; None ; -12.700 ns ; a[2] ; r[4] ; clk ;
; N/A ; None ; -12.900 ns ; a[4] ; r[7] ; clk ;
; N/A ; None ; -12.900 ns ; a[4] ; carryout ; clk ;
; N/A ; None ; -12.900 ns ; a[4] ; carryout~1 ; clk ;
; N/A ; None ; -12.900 ns ; ci ; r[2] ; clk ;
; N/A ; None ; -14.300 ns ; b[3] ; r[6] ; clk ;
; N/A ; None ; -14.300 ns ; b[1] ; r[4] ; clk ;
; N/A ; None ; -14.300 ns ; b[0] ; r[3] ; clk ;
; N/A ; None ; -14.400 ns ; a[3] ; r[6] ; clk ;
; N/A ; None ; -14.400 ns ; b[2] ; r[5] ; clk ;
; N/A ; None ; -14.500 ns ; a[0] ; r[3] ; clk ;
; N/A ; None ; -14.900 ns ; a[1] ; r[4] ; clk ;
; N/A ; None ; -15.000 ns ; a[2] ; r[5] ; clk ;
; N/A ; None ; -15.100 ns ; ci ; r[3] ; clk ;
; N/A ; None ; -16.300 ns ; b[3] ; r[7] ; clk ;
; N/A ; None ; -16.300 ns ; b[3] ; carryout ; clk ;
; N/A ; None ; -16.300 ns ; b[3] ; carryout~1 ; clk ;
; N/A ; None ; -16.400 ns ; a[3] ; r[7] ; clk ;
; N/A ; None ; -16.400 ns ; a[3] ; carryout ; clk ;
; N/A ; None ; -16.400 ns ; a[3] ; carryout~1 ; clk ;
; N/A ; None ; -16.600 ns ; b[2] ; r[6] ; clk ;
; N/A ; None ; -16.600 ns ; b[1] ; r[5] ; clk ;
; N/A ; None ; -17.200 ns ; a[2] ; r[6] ; clk ;
; N/A ; None ; -17.200 ns ; a[1] ; r[5] ; clk ;
; N/A ; None ; -18.200 ns ; b[0] ; r[4] ; clk ;
; N/A ; None ; -18.400 ns ; a[0] ; r[4] ; clk ;
; N/A ; None ; -18.600 ns ; b[2] ; r[7] ; clk ;
; N/A ; None ; -18.600 ns ; b[2] ; carryout ; clk ;
; N/A ; None ; -18.600 ns ; b[2] ; carryout~1 ; clk ;
; N/A ; None ; -18.800 ns ; b[1] ; r[6] ; clk ;
; N/A ; None ; -19.000 ns ; ci ; r[4] ; clk ;
; N/A ; None ; -19.200 ns ; a[2] ; r[7] ; clk ;
; N/A ; None ; -19.200 ns ; a[2] ; carryout ; clk ;
; N/A ; None ; -19.200 ns ; a[2] ; carryout~1 ; clk ;
; N/A ; None ; -19.400 ns ; a[1] ; r[6] ; clk ;
; N/A ; None ; -20.500 ns ; b[0] ; r[5] ; clk ;
; N/A ; None ; -20.700 ns ; a[0] ; r[5] ; clk ;
; N/A ; None ; -20.800 ns ; b[1] ; r[7] ; clk ;
; N/A ; None ; -20.800 ns ; b[1] ; carryout ; clk ;
; N/A ; None ; -20.800 ns ; b[1] ; carryout~1 ; clk ;
; N/A ; None ; -21.300 ns ; ci ; r[5] ; clk ;
; N/A ; None ; -21.400 ns ; a[1] ; r[7] ; clk ;
; N/A ; None ; -21.400 ns ; a[1] ; carryout ; clk ;
; N/A ; None ; -21.400 ns ; a[1] ; carryout~1 ; clk ;
; N/A ; None ; -22.700 ns ; b[0] ; r[6] ; clk ;
; N/A ; None ; -22.900 ns ; a[0] ; r[6] ; clk ;
; N/A ; None ; -23.500 ns ; ci ; r[6] ; clk ;
; N/A ; None ; -24.700 ns ; b[0] ; r[7] ; clk ;
; N/A ; None ; -24.700 ns ; b[0] ; carryout ; clk ;
; N/A ; None ; -24.700 ns ; b[0] ; carryout~1 ; clk ;
; N/A ; None ; -24.900 ns ; a[0] ; r[7] ; clk ;
; N/A ; None ; -24.900 ns ; a[0] ; carryout ; clk ;
; N/A ; None ; -24.900 ns ; a[0] ; carryout~1 ; clk ;
; N/A ; None ; -25.500 ns ; ci ; r[7] ; clk ;
; N/A ; None ; -25.500 ns ; ci ; carryout ; clk ;
; N/A ; None ; -25.500 ns ; ci ; carryout~1 ; clk ;
+---------------+-------------+------------+-------+------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Feb 22 13:57:54 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off add1 -c add1
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "r[7]" (data pin = "sign1", clock pin = "clk") is 27.400 ns
Info: + Longest pin to register delay is 28.600 ns
Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_95; Fanout = 17; PIN Node = 'sign1'
Info: 2: + IC(5.400 ns) + CELL(1.900 ns) = 10.400 ns; Loc. = LC2_B35; Fanout = 2; COMB Node = 'co[0]~662'
Info: 3: + IC(1.900 ns) + CELL(2.000 ns) = 14.300 ns; Loc. = LC5_B47; Fanout = 2; COMB Node = 'co[1]~663'
Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 16.500 ns; Loc. = LC6_B47; Fanout = 2; COMB Node = 'co[2]~664'
Info: 5: + IC(0.200 ns) + CELL(2.000 ns) = 18.700 ns; Loc. = LC3_B47; Fanout = 2; COMB Node = 'co[3]~665'
Info: 6: + IC(2.000 ns) + CELL(2.000 ns) = 22.700 ns; Loc. = LC1_B34; Fanout = 2; COMB Node = 'co[4]~666'
Info: 7: + IC(0.200 ns) + CELL(2.000 ns) = 24.900 ns; Loc. = LC2_B34; Fanout = 2; COMB Node = 'co[5]~667'
Info: 8: + IC(0.200 ns) + CELL(2.000 ns) = 27.100 ns; Loc. = LC6_B34; Fanout = 3; COMB Node = 'co[6]~668'
Info: 9: + IC(0.200 ns) + CELL(1.300 ns) = 28.600 ns; Loc. = LC7_B34; Fanout = 4; REG Node = 'r[7]'
Info: Total cell delay = 18.300 ns ( 63.99 % )
Info: Total interconnect delay = 10.300 ns ( 36.01 % )
Info: + Micro setup delay of destination is 0.700 ns
Info: - Shortest clock path from clock "clk" to destination register is 1.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 10; CLK Node = 'clk'
Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_B34; Fanout = 4; REG Node = 'r[7]'
Info: Total cell delay = 0.500 ns ( 26.32 % )
Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: tco from clock "clk" to destination pin "z" through register "r[4]" is 19.800 ns
Info: + Longest clock path from clock "clk" to source register is 1.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 10; CLK Node = 'clk'
Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_B40; Fanout = 2; REG Node = 'r[4]'
Info: Total cell delay = 0.500 ns ( 26.32 % )
Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Longest register to pin delay is 16.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B40; Fanout = 2; REG Node = 'r[4]'
Info: 2: + IC(1.800 ns) + CELL(1.500 ns) = 3.300 ns; Loc. = LC6_B35; Fanout = 1; COMB Node = 'reduce_nor~52'
Info: 3: + IC(0.000 ns) + CELL(1.900 ns) = 5.200 ns; Loc. = LC7_B35; Fanout = 1; COMB Node = 'reduce_nor~49'
Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.100 ns; Loc. = LC3_B35; Fanout = 1; COMB Node = 'z~0'
Info: 5: + IC(1.200 ns) + CELL(8.500 ns) = 16.800 ns; Loc. = PIN_191; Fanout = 0; PIN Node = 'z'
Info: Total cell delay = 13.600 ns ( 80.95 % )
Info: Total interconnect delay = 3.200 ns ( 19.05 % )
Info: Longest tpd from source pin "sign1" to destination pin "v" is 22.300 ns
Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_95; Fanout = 17; PIN Node = 'sign1'
Info: 2: + IC(5.500 ns) + CELL(1.900 ns) = 10.500 ns; Loc. = LC2_B37; Fanout = 1; COMB Node = 'b_data[7]~44'
Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 12.600 ns; Loc. = LC1_B37; Fanout = 1; COMB Node = 'process1~3'
Info: 4: + IC(1.200 ns) + CELL(8.500 ns) = 22.300 ns; Loc. = PIN_192; Fanout = 0; PIN Node = 'v'
Info: Total cell delay = 15.400 ns ( 69.06 % )
Info: Total interconnect delay = 6.900 ns ( 30.94 % )
Info: th for register "r[6]" (data pin = "a[6]", clock pin = "clk") is -5.100 ns
Info: + Longest clock path from clock "clk" to destination register is 1.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 10; CLK Node = 'clk'
Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_B34; Fanout = 2; REG Node = 'r[6]'
Info: Total cell delay = 0.500 ns ( 26.32 % )
Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: + Micro hold delay of destination is 0.900 ns
Info: - Shortest pin to register delay is 7.900 ns
Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_74; Fanout = 2; PIN Node = 'a[6]'
Info: 2: + IC(3.800 ns) + CELL(1.000 ns) = 7.900 ns; Loc. = LC3_B34; Fanout = 2; REG Node = 'r[6]'
Info: Total cell delay = 4.100 ns ( 51.90 % )
Info: Total interconnect delay = 3.800 ns ( 48.10 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Wed Feb 22 13:57:56 2006
Info: Elapsed time: 00:00:02
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -