add1.fit.summary

8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器8位全加器

Flow Status : Successful - Wed Feb 22 13:57:50 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : add1
Top-level Entity Name : add1
Family : ACEX1K
Device : EP1K100QC208-3
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 23 / 4,992 ( < 1 % )
Total pins : 33 / 147 ( 22 % )
Total memory bits : 0 / 49,152 ( 0 % )
Total PLLs : 0