📄 clock.rpt
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_EQ065 = h0 & !_LC8_B10
# g0 & _LC8_B10;
-- Node name is ':813'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = LCELL( _EQ066);
_EQ066 = c0 & _LC2_B10
# _LC2_B1 & !_LC2_B10;
-- Node name is ':816'
-- Equation name is '_LC5_B3', type is buried
_LC5_B3 = LCELL( _EQ067);
_EQ067 = _LC4_B3 & !_LC7_B18
# e0 & _LC7_B18;
-- Node name is ':819'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = LCELL( _EQ068);
_EQ068 = !_LC4_B10 & _LC5_B3
# d0 & _LC4_B10;
-- Node name is ':822'
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = LCELL( _EQ069);
_EQ069 = _LC6_B3 & !_LC6_B10
# c0 & _LC6_B10;
-- Node name is ':825'
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = LCELL( _EQ070);
_EQ070 = !_LC3_B10 & _LC7_B3
# b0 & _LC3_B10;
-- Node name is ':1105'
-- Equation name is '_LC5_B12', type is buried
_LC5_B12 = LCELL( _EQ071);
_EQ071 = !a3
# !a0 & !a1 & !a2;
-- Node name is '~1107~1'
-- Equation name is '~1107~1', location is LC2_B12, type is buried.
-- synthesized logic cell
_LC2_B12 = LCELL( _EQ072);
_EQ072 = !a1 & !a2;
-- Node name is '~1244~1'
-- Equation name is '~1244~1', location is LC2_B6, type is buried.
-- synthesized logic cell
_LC2_B6 = LCELL( _EQ073);
_EQ073 = a0 & b0 & !b1 & b2;
-- Node name is ':1244'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = LCELL( _EQ074);
_EQ074 = a3 & !b3 & _LC2_B6 & _LC2_B12;
-- Node name is ':1459'
-- Equation name is '_LC8_B20', type is buried
_LC8_B20 = LCELL( _EQ075);
_EQ075 = !d0 & d1 & !d2 & d3;
-- Node name is '~1565~1'
-- Equation name is '~1565~1', location is LC6_B11, type is buried.
-- synthesized logic cell
_LC6_B11 = LCELL( _EQ076);
_EQ076 = e3
# d2
# !d3;
-- Node name is '~1565~2'
-- Equation name is '~1565~2', location is LC6_B14, type is buried.
-- synthesized logic cell
_LC6_B14 = LCELL( _EQ077);
_EQ077 = !d0
# e1
# !e2;
-- Node name is ':1565'
-- Equation name is '_LC4_B14', type is buried
!_LC4_B14 = _LC4_B14~NOT;
_LC4_B14~NOT = LCELL( _EQ078);
_EQ078 = d1
# !e0
# _LC6_B11
# _LC6_B14;
-- Node name is '~1674~1'
-- Equation name is '~1674~1', location is LC4_B20, type is buried.
-- synthesized logic cell
_LC4_B20 = LCELL( _EQ079);
_EQ079 = !_LC4_B14 & !_LC8_B20;
-- Node name is ':1685'
-- Equation name is '_LC7_B1', type is buried
!_LC7_B1 = _LC7_B1~NOT;
_LC7_B1~NOT = LCELL( _EQ080);
_EQ080 = g2
# !g3
# !g1
# g0;
-- Node name is '~1791~1'
-- Equation name is '~1791~1', location is LC7_B2, type is buried.
-- synthesized logic cell
_LC7_B2 = LCELL( _EQ081);
_EQ081 = h0
# !h1
# h2
# h3;
-- Node name is ':1791'
-- Equation name is '_LC2_B9', type is buried
!_LC2_B9 = _LC2_B9~NOT;
_LC2_B9~NOT = LCELL( _EQ082);
_EQ082 = !_LC6_B1
# _LC7_B2
# g2
# g3;
-- Node name is '~1842~1'
-- Equation name is '~1842~1', location is LC4_B12, type is buried.
-- synthesized logic cell
_LC4_B12 = LCELL( _EQ083);
_EQ083 = !_LC1_B6 & _LC5_B12
# _LC2_B9;
-- Node name is ':2543'
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = LCELL( _EQ084);
_EQ084 = !LED70 & !LED71 & LED72 & !LED73;
-- Node name is ':2567'
-- Equation name is '_LC5_B8', type is buried
!_LC5_B8 = _LC5_B8~NOT;
_LC5_B8~NOT = LCELL( _EQ085);
_EQ085 = LED73
# LED70
# !LED71
# LED72;
-- Node name is '~2570~1'
-- Equation name is '~2570~1', location is LC3_B8, type is buried.
-- synthesized logic cell
_LC3_B8 = LCELL( _EQ086);
_EQ086 = LED70 & LED71 & !LED72 & !LED73
# !LED70 & !LED71 & LED72 & !LED73;
-- Node name is ':2591'
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = LCELL( _EQ087);
_EQ087 = !LED70 & !LED71 & !LED72 & !LED73;
-- Node name is '~2596~1'
-- Equation name is '~2596~1', location is LC2_B8, type is buried.
-- synthesized logic cell
!_LC2_B8 = _LC2_B8~NOT;
_LC2_B8~NOT = LCELL( _EQ088);
_EQ088 = !LED71 & !LED72 & !LED73;
-- Node name is ':2596'
-- Equation name is '_LC6_B8', type is buried
_LC6_B8 = LCELL( _EQ089);
_EQ089 = !LED70 & LED71 & !LED73
# LED71 & !LED72 & !LED73
# !LED70 & LED72 & !LED73
# LED70 & !LED71 & LED72
# !LED71 & !LED72 & LED73
# LED70 & !LED71 & LED73;
-- Node name is ':2633'
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = LCELL( _EQ090);
_EQ090 = _LC6_B7 & _LC8_B7
# _LC2_B7 & _LC6_B7
# _LC1_B7;
-- Node name is '~2635~1'
-- Equation name is '~2635~1', location is LC6_B7, type is buried.
-- synthesized logic cell
!_LC6_B7 = _LC6_B7~NOT;
_LC6_B7~NOT = LCELL( _EQ091);
_EQ091 = LED70 & !LED72 & !LED73
# LED71 & !LED72 & !LED73;
-- Node name is ':2672'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = LCELL( _EQ092);
_EQ092 = !LED70 & !LED72 & !LED73
# !LED70 & !LED71 & !LED72
# !LED70 & LED71 & !LED73;
-- Node name is ':2696'
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = LCELL( _EQ093);
_EQ093 = LED70 & !LED71 & LED72 & !LED73
# !LED70 & LED71 & LED72 & !LED73
# !LED71 & !LED72 & LED73;
-- Node name is ':2711'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = LCELL( _EQ094);
_EQ094 = LED71 & !LED72 & !LED73
# !LED70 & !LED72 & !LED73
# LED70 & !LED71 & LED72 & !LED73
# !LED70 & LED71 & !LED73
# !LED70 & !LED71 & !LED72
# !LED71 & !LED72 & LED73;
-- Node name is ':2750'
-- Equation name is '_LC7_B8', type is buried
_LC7_B8 = LCELL( _EQ095);
_EQ095 = !_LC2_B8
# _LC3_B8 & !_LC5_B8
# !_LC5_B8 & _LC8_B8;
-- Node name is ':2779'
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = LCELL( _EQ096);
_EQ096 = !LED71 & !LED72 & LED73
# LED70 & LED71 & LED72 & !LED73;
-- Node name is ':2789'
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = LCELL( _EQ097);
_EQ097 = _LC1_B7
# _LC2_B7
# !_LC6_B7
# _LC7_B7;
-- Node name is ':2813'
-- Equation name is '_LC8_B8', type is buried
_LC8_B8 = LCELL( _EQ098);
_EQ098 = LED71 & LED72 & !LED73
# !LED71 & !LED72 & LED73
# LED70 & LED72 & !LED73;
-- Node name is ':2828'
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = LCELL( _EQ099);
_EQ099 = !LED70 & !LED72 & !LED73
# LED70 & LED72 & !LED73
# !LED70 & !LED71 & !LED72
# !LED71 & !LED72 & LED73
# LED71 & !LED73;
Project Information f:\新建文件夹\0305632tyx\clock.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,182K
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