📄 clock.rpt
字号:
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\新建文件夹\0305632tyx\clock.rpt
clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 06 AND2 0 2 0 1 |LPM_ADD_SUB:1155|addcore:adder|:55
- 8 - B 06 AND2 0 3 0 1 |LPM_ADD_SUB:1155|addcore:adder|:59
- 6 - B 20 AND2 0 2 0 1 |LPM_ADD_SUB:1257|addcore:adder|:55
- 7 - B 20 AND2 0 3 0 1 |LPM_ADD_SUB:1257|addcore:adder|:59
- 7 - B 14 AND2 0 2 0 1 |LPM_ADD_SUB:1476|addcore:adder|:55
- 8 - B 14 AND2 0 3 0 1 |LPM_ADD_SUB:1476|addcore:adder|:59
- 6 - B 01 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1578|addcore:adder|:55
- 6 - B 09 AND2 0 2 0 1 |LPM_ADD_SUB:1578|addcore:adder|:59
- 1 - B 09 AND2 0 2 0 1 |LPM_ADD_SUB:1702|addcore:adder|:55
- 2 - B 02 AND2 0 3 0 1 |LPM_ADD_SUB:1702|addcore:adder|:59
- 7 - B 12 AND2 0 2 0 1 |LPM_ADD_SUB:1804|addcore:adder|:55
- 1 - B 10 DFFE + 0 3 1 0 :10
- 8 - B 01 DFFE + 0 1 1 0 :12
- 4 - B 02 DFFE + 0 1 1 0 :14
- 2 - C 02 DFFE + 0 1 1 0 :16
- 2 - B 03 DFFE + 0 1 1 0 :18
- 1 - C 03 DFFE + 0 1 1 0 :20
- 1 - B 04 DFFE + 0 1 1 0 :22
- 4 - B 05 DFFE + 0 1 1 0 :24
- 5 - B 10 DFFE + 0 2 0 8 SLIP2 (:26)
- 2 - B 18 DFFE + 0 1 0 9 SLIP1 (:27)
- 8 - B 18 DFFE + 0 0 0 10 SLIP0 (:28)
- 3 - B 12 DFFE + 0 3 0 3 a3 (:29)
- 6 - B 12 DFFE + 0 3 0 4 a2 (:30)
- 8 - B 12 DFFE + 0 2 0 5 a1 (:31)
- 1 - B 12 DFFE + 0 2 0 6 a0 (:32)
- 2 - B 05 DFFE + 0 3 0 13 LED73 (:33)
- 1 - B 05 DFFE + 0 3 0 13 LED72 (:34)
- 3 - B 05 DFFE + 0 3 0 13 LED71 (:35)
- 1 - B 03 DFFE + 0 3 0 12 LED70 (:36)
- 3 - B 06 DFFE + 0 3 0 2 b3 (:37)
- 6 - B 06 DFFE + 0 3 0 3 b2 (:38)
- 4 - B 06 DFFE + 0 3 0 4 b1 (:39)
- 5 - B 06 DFFE + 0 2 0 5 b0 (:40)
- 5 - B 02 DFFE + 0 0 0 3 c3 (:41)
- 3 - B 03 DFFE + 0 1 0 2 c0 (:44)
- 2 - B 20 DFFE + 0 3 0 3 d3 (:45)
- 5 - B 20 DFFE + 0 3 0 4 d2 (:46)
- 3 - B 20 DFFE + 0 3 0 5 d1 (:47)
- 1 - B 20 DFFE + 0 2 0 6 d0 (:48)
- 1 - B 14 DFFE + 0 3 0 2 e3 (:49)
- 5 - B 14 DFFE + 0 3 0 3 e2 (:50)
- 2 - B 14 DFFE + 0 3 0 4 e1 (:51)
- 3 - B 14 DFFE + 0 2 0 5 e0 (:52)
- 7 - B 09 DFFE + 0 3 0 3 g3 (:57)
- 3 - B 09 DFFE + 0 3 0 4 g2 (:58)
- 1 - B 01 DFFE + 0 3 0 3 g1 (:59)
- 4 - B 01 DFFE + 0 2 0 4 g0 (:60)
- 6 - B 02 DFFE + 0 3 0 2 h3 (:61)
- 5 - B 09 DFFE + 0 3 0 3 h2 (:62)
- 4 - B 09 DFFE + 0 3 0 4 h1 (:63)
- 8 - B 09 DFFE + 0 2 0 5 h0 (:64)
- 8 - B 10 AND2 0 3 0 5 :501
- 2 - B 10 AND2 0 3 0 6 :511
- 7 - B 18 AND2 0 3 0 5 :521
- 4 - B 10 AND2 0 3 0 5 :531
- 6 - B 10 AND2 0 3 0 6 :541
- 3 - B 10 AND2 0 3 0 5 :551
- 7 - B 10 AND2 0 3 0 5 :561
- 1 - B 02 AND2 0 2 0 2 :742
- 3 - B 02 OR2 0 4 0 1 :743
- 7 - B 11 OR2 0 4 0 1 :744
- 5 - B 11 AND2 0 2 0 2 :751
- 8 - B 11 OR2 0 4 0 1 :752
- 1 - B 11 OR2 0 4 0 1 :753
- 8 - B 02 OR2 0 4 0 1 :767
- 2 - B 11 OR2 0 4 0 1 :768
- 3 - B 11 OR2 0 4 0 1 :776
- 4 - B 11 OR2 0 4 0 1 :777
- 5 - B 01 OR2 0 3 0 1 :786
- 3 - B 01 OR2 0 4 0 1 :792
- 5 - B 05 OR2 0 3 0 1 :795
- 6 - B 05 OR2 0 4 0 1 :801
- 2 - B 01 OR2 0 3 0 1 :810
- 4 - B 03 OR2 0 3 0 1 :813
- 5 - B 03 OR2 0 3 0 1 :816
- 6 - B 03 OR2 0 3 0 1 :819
- 7 - B 03 OR2 0 3 0 1 :822
- 8 - B 03 OR2 0 3 0 1 :825
- 5 - B 12 OR2 0 4 0 6 :1105
- 2 - B 12 AND2 s 0 2 0 1 ~1107~1
- 2 - B 06 AND2 s 0 4 0 1 ~1244~1
- 1 - B 06 AND2 0 4 0 9 :1244
- 8 - B 20 AND2 0 4 0 5 :1459
- 6 - B 11 OR2 s 0 3 0 1 ~1565~1
- 6 - B 14 OR2 s 0 3 0 1 ~1565~2
- 4 - B 14 OR2 ! 0 4 0 9 :1565
- 4 - B 20 AND2 s 0 2 0 4 ~1674~1
- 7 - B 01 OR2 ! 0 4 0 8 :1685
- 7 - B 02 OR2 s 0 4 0 1 ~1791~1
- 2 - B 09 OR2 ! 0 4 0 6 :1791
- 4 - B 12 OR2 s 0 3 0 3 ~1842~1
- 2 - B 07 AND2 0 4 0 2 :2543
- 5 - B 08 OR2 ! 0 4 0 1 :2567
- 3 - B 08 OR2 s 0 4 0 1 ~2570~1
- 1 - B 07 AND2 0 4 0 2 :2591
- 2 - B 08 AND2 s ! 0 3 0 1 ~2596~1
- 6 - B 08 OR2 0 4 1 0 :2596
- 4 - B 07 OR2 0 4 1 0 :2633
- 6 - B 07 OR2 s ! 0 4 0 2 ~2635~1
- 1 - B 08 OR2 0 4 1 0 :2672
- 8 - B 07 OR2 0 4 0 1 :2696
- 4 - B 08 OR2 0 4 1 0 :2711
- 7 - B 08 OR2 0 4 1 0 :2750
- 7 - B 07 OR2 0 4 0 1 :2779
- 5 - B 07 OR2 0 4 1 0 :2789
- 8 - B 08 OR2 0 4 0 1 :2813
- 3 - B 07 OR2 0 4 1 0 :2828
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\新建文件夹\0305632tyx\clock.rpt
clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 22/ 96( 22%) 34/ 48( 70%) 2/ 48( 4%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 1/ 96( 1%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\新建文件夹\0305632tyx\clock.rpt
clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 26 CLK1
INPUT 15 CLK2
Device-Specific Information: f:\新建文件夹\0305632tyx\clock.rpt
clock
** EQUATIONS **
CLK1 : INPUT;
CLK2 : INPUT;
-- Node name is ':32' = 'a0'
-- Equation name is 'a0', location is LC1_B12, type is buried.
a0 = DFFE( _EQ001, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ001 = !a0 & _LC5_B12
# !a0 & _LC2_B9;
-- Node name is ':31' = 'a1'
-- Equation name is 'a1', location is LC8_B12, type is buried.
a1 = DFFE( _EQ002, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ002 = !a0 & a1 & _LC4_B12
# a0 & !a1 & _LC4_B12;
-- Node name is ':30' = 'a2'
-- Equation name is 'a2', location is LC6_B12, type is buried.
a2 = DFFE( _EQ003, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ003 = !a1 & a2 & _LC4_B12
# !a0 & a2 & _LC4_B12
# a0 & a1 & !a2 & _LC4_B12;
-- Node name is ':29' = 'a3'
-- Equation name is 'a3', location is LC3_B12, type is buried.
a3 = DFFE( _EQ004, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ004 = !a2 & a3 & _LC4_B12
# a3 & _LC4_B12 & !_LC7_B12
# a2 & !a3 & _LC4_B12 & _LC7_B12;
-- Node name is ':40' = 'b0'
-- Equation name is 'b0', location is LC5_B6, type is buried.
b0 = DFFE( _EQ005, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ005 = !b0 & !_LC1_B6 & !_LC5_B12
# b0 & !_LC1_B6 & _LC5_B12;
-- Node name is ':39' = 'b1'
-- Equation name is 'b1', location is LC4_B6, type is buried.
b1 = DFFE( _EQ006, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ006 = b1 & !_LC1_B6 & _LC5_B12
# !b0 & b1 & !_LC1_B6
# b0 & !b1 & !_LC1_B6 & !_LC5_B12;
-- Node name is ':38' = 'b2'
-- Equation name is 'b2', location is LC6_B6, type is buried.
b2 = DFFE( _EQ007, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ007 = b2 & !_LC1_B6 & _LC5_B12
# b2 & !_LC1_B6 & !_LC7_B6
# !b2 & !_LC1_B6 & !_LC5_B12 & _LC7_B6;
-- Node name is ':37' = 'b3'
-- Equation name is 'b3', location is LC3_B6, type is buried.
b3 = DFFE( _EQ008, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ008 = b3 & !_LC1_B6 & _LC5_B12
# b3 & !_LC1_B6 & !_LC8_B6
# !b3 & !_LC1_B6 & !_LC5_B12 & _LC8_B6;
-- Node name is 'CHOICE0'
-- Equation name is 'CHOICE0', type is output
CHOICE0 = _LC4_B5;
-- Node name is 'CHOICE1'
-- Equation name is 'CHOICE1', type is output
CHOICE1 = _LC1_B4;
-- Node name is 'CHOICE2'
-- Equation name is 'CHOICE2', type is output
CHOICE2 = _LC1_C3;
-- Node name is 'CHOICE3'
-- Equation name is 'CHOICE3', type is output
CHOICE3 = _LC2_B3;
-- Node name is 'CHOICE4'
-- Equation name is 'CHOICE4', type is output
CHOICE4 = _LC2_C2;
-- Node name is 'CHOICE5'
-- Equation name is 'CHOICE5', type is output
CHOICE5 = _LC4_B2;
-- Node name is 'CHOICE6'
-- Equation name is 'CHOICE6', type is output
CHOICE6 = _LC8_B1;
-- Node name is 'CHOICE7'
-- Equation name is 'CHOICE7', type is output
CHOICE7 = _LC1_B10;
-- Node name is ':44' = 'c0'
-- Equation name is 'c0', location is LC3_B3, type is buried.
c0 = DFFE( _EQ009, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ009 = !c0 & c3;
-- Node name is ':41' = 'c3'
-- Equation name is 'c3', location is LC5_B2, type is buried.
c3 = DFFE( VCC, GLOBAL( CLK1), VCC, VCC, VCC);
-- Node name is 'DOUT0'
-- Equation name is 'DOUT0', type is output
DOUT0 = _LC3_B7;
-- Node name is 'DOUT1'
-- Equation name is 'DOUT1', type is output
DOUT1 = _LC5_B7;
-- Node name is 'DOUT2'
-- Equation name is 'DOUT2', type is output
DOUT2 = _LC7_B8;
-- Node name is 'DOUT3'
-- Equation name is 'DOUT3', type is output
DOUT3 = _LC4_B8;
-- Node name is 'DOUT4'
-- Equation name is 'DOUT4', type is output
DOUT4 = _LC1_B8;
-- Node name is 'DOUT5'
-- Equation name is 'DOUT5', type is output
DOUT5 = _LC4_B7;
-- Node name is 'DOUT6'
-- Equation name is 'DOUT6', type is output
DOUT6 = _LC6_B8;
-- Node name is ':48' = 'd0'
-- Equation name is 'd0', location is LC1_B20, type is buried.
d0 = DFFE( _EQ010, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ010 = d0 & !_LC1_B6 & _LC4_B20
# !d0 & _LC1_B6 & _LC4_B20;
-- Node name is ':47' = 'd1'
-- Equation name is 'd1', location is LC3_B20, type is buried.
d1 = DFFE( _EQ011, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ011 = !d0 & d1 & _LC4_B20
# d0 & !d1 & _LC1_B6 & _LC4_B20
# d1 & !_LC1_B6 & _LC4_B20;
-- Node name is ':46' = 'd2'
-- Equation name is 'd2', location is LC5_B20, type is buried.
d2 = DFFE( _EQ012, GLOBAL( CLK1), VCC, VCC, VCC);
_EQ012 = d2 & _LC4_B20 & !_LC6_B20
# !d2 & _LC1_B6 & _LC4_B20 & _LC6_B20
# d2 & !_LC1_B6 & _LC4_B20;
-- Node name is ':45' = 'd3'
-- Equation name is 'd3', location is LC2_B20, type is buried.
d3 = DFFE( _EQ013, GLOBAL( CLK1), VCC, VCC, VCC);
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