📄 light.rpt
字号:
light
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 11 DFFE + 0 3 1 0 :2
- 1 - A 14 DFFE + 0 3 1 0 :4
- 1 - A 15 DFFE + 0 3 1 0 :6
- 4 - A 15 DFFE + 0 3 1 0 :8
- 1 - A 17 DFFE + 0 3 1 0 :10
- 4 - A 17 DFFE + 0 3 1 0 :12
- 2 - A 19 DFFE + 0 3 1 0 :14
- 8 - A 19 DFFE + 0 3 1 0 :16
- 5 - A 19 DFFE + 0 2 0 8 SEL2 (:18)
- 1 - A 19 DFFE + 0 1 0 9 SEL1 (:19)
- 6 - A 19 DFFE + 0 0 0 10 SEL0 (:20)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\0305632tyx\light.rpt
light
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\0305632tyx\light.rpt
light
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 CLK
Device-Specific Information: e:\0305632tyx\light.rpt
light
** EQUATIONS **
CLK : INPUT;
-- Node name is ':20' = 'SEL0'
-- Equation name is 'SEL0', location is LC6_A19, type is buried.
SEL0 = DFFE(!SEL0, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':19' = 'SEL1'
-- Equation name is 'SEL1', location is LC1_A19, type is buried.
SEL1 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = SEL0 & !SEL1
# !SEL0 & SEL1;
-- Node name is ':18' = 'SEL2'
-- Equation name is 'SEL2', location is LC5_A19, type is buried.
SEL2 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = !SEL0 & SEL2
# !SEL1 & SEL2
# SEL0 & SEL1 & !SEL2;
-- Node name is 'Y0'
-- Equation name is 'Y0', type is output
Y0 = _LC8_A19;
-- Node name is 'Y1'
-- Equation name is 'Y1', type is output
Y1 = _LC2_A19;
-- Node name is 'Y2'
-- Equation name is 'Y2', type is output
Y2 = _LC4_A17;
-- Node name is 'Y3'
-- Equation name is 'Y3', type is output
Y3 = _LC1_A17;
-- Node name is 'Y4'
-- Equation name is 'Y4', type is output
Y4 = _LC4_A15;
-- Node name is 'Y5'
-- Equation name is 'Y5', type is output
Y5 = _LC1_A15;
-- Node name is 'Y6'
-- Equation name is 'Y6', type is output
Y6 = _LC1_A14;
-- Node name is 'Y7'
-- Equation name is 'Y7', type is output
Y7 = _LC1_A11;
-- Node name is ':2'
-- Equation name is '_LC1_A11', type is buried
_LC1_A11 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !SEL0 & !SEL1 & !SEL2;
-- Node name is ':4'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = SEL0 & !SEL1 & !SEL2;
-- Node name is ':6'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = !SEL0 & SEL1 & !SEL2;
-- Node name is ':8'
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = SEL0 & SEL1 & !SEL2;
-- Node name is ':10'
-- Equation name is '_LC1_A17', type is buried
_LC1_A17 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = !SEL0 & !SEL1 & SEL2;
-- Node name is ':12'
-- Equation name is '_LC4_A17', type is buried
_LC4_A17 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = SEL0 & !SEL1 & SEL2;
-- Node name is ':14'
-- Equation name is '_LC2_A19', type is buried
_LC2_A19 = DFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = !SEL0 & SEL1 & SEL2;
-- Node name is ':16'
-- Equation name is '_LC8_A19', type is buried
_LC8_A19 = DFFE( _EQ010, GLOBAL( CLK), VCC, VCC, VCC);
_EQ010 = SEL0 & SEL1 & SEL2;
Project Information e:\0305632tyx\light.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,596K
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