📄 speaker.rpt
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Project Information e:\0305632tyx\speaker.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 01/03/2008 20:16:40
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was unsuccessful
SPEAKER
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
speaker EPF10K10LC84-4 12 1 0 0 28 No Fit
User Pins: 12 1 0
Project Information e:\0305632tyx\speaker.rpt
** PROJECT COMPILATION MESSAGES **
Error: No fit found, generating Report File
(See individual chip error summaries for additional information)
Project Information e:\0305632tyx\speaker.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
speaker@3 --------- clk
speaker@30 --------- spks
speaker@58 --------- tone0
speaker@59 --------- tone1
speaker@59 --------- tone2
speaker@60 --------- tone3
speaker@61 --------- tone4
speaker@62 --------- tone5
speaker@64 --------- tone6
speaker@65 --------- tone7
speaker@66 --------- tone8
speaker@67 --------- tone9
speaker@69 --------- tone10
Project Information e:\0305632tyx\speaker.rpt
** FILE HIERARCHY **
|lpm_add_sub:53|
|lpm_add_sub:53|addcore:adder|
|lpm_add_sub:53|altshift:result_ext_latency_ffs|
|lpm_add_sub:53|altshift:carry_ext_latency_ffs|
|lpm_add_sub:53|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:166|
|lpm_add_sub:166|addcore:adder|
|lpm_add_sub:166|altshift:result_ext_latency_ffs|
|lpm_add_sub:166|altshift:carry_ext_latency_ffs|
|lpm_add_sub:166|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\0305632tyx\speaker.rpt
speaker
***** Logic for device 'speaker' contains errors -- see ERROR SUMMARY.
Device: EPF10K10LC84-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
Device-Specific Information: e:\0305632tyx\speaker.rpt
speaker
** ERROR SUMMARY **
Error: Can't put both 'tone1' and 'tone2' on pin 59
Device-Specific Information: e:\0305632tyx\speaker.rpt
speaker
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 0/53 ( 0%)
Total logic cells used: 0/576 ( 0%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 2.85/4 ( 71%)
Total fan-in: 80/2304 ( 3%)
Total input pins required: 12
Total input I/O cell registers required: 0
Total output pins required: 1
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 28
Total flipflops required: 18
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Device-Specific Information: e:\0305632tyx\speaker.rpt
speaker
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
3 - - - 12 INPUT 0 0 0 4 clk
58 - - C -- INPUT 0 0 0 1 tone0
59 - - C -- INPUT 0 0 0 1 tone1
59 - - C -- INPUT 0 0 0 1 tone2
60 - - C -- INPUT 0 0 0 1 tone3
61 - - C -- INPUT 0 0 0 1 tone4
62 - - C -- INPUT 0 0 0 1 tone5
64 - - B -- INPUT 0 0 0 1 tone6
65 - - B -- INPUT 0 0 0 1 tone7
66 - - B -- INPUT 0 0 0 1 tone8
67 - - B -- INPUT 0 0 0 1 tone9
69 - - A -- INPUT 0 0 0 1 tone10
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\0305632tyx\speaker.rpt
speaker
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
30 - - C -- OUTPUT 0 1 0 0 spks
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\0305632tyx\speaker.rpt
speaker
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- ?? - ? ? AND2 0 2 0 2 |LPM_ADD_SUB:166|addcore:adder|:87
- ?? - ? ? AND2 0 2 0 2 |LPM_ADD_SUB:166|addcore:adder|:91
- ?? - ? ? AND2 0 2 0 2 |LPM_ADD_SUB:166|addcore:adder|:95
- ?? - ? ? AND2 0 2 0 2 |LPM_ADD_SUB:166|addcore:adder|:99
- ?? - ? ? AND2 0 2 0 2 |LPM_ADD_SUB:166|addcore:adder|:103
- ?? - ? ? AND2 0 2 0 2 |LPM_ADD_SUB:166|addcore:adder|:107
- ?? - ? ? AND2 0 2 0 3 |LPM_ADD_SUB:166|addcore:adder|:111
- ?? - ? ? AND2 0 2 0 3 |LPM_ADD_SUB:166|addcore:adder|:115
- ?? - ? ? DFFE 0 2 1 0 :13
- ?? - ? ? DFFE 0 5 0 2 fullspks (:16)
- ?? - ? ? DFFE 1 4 0 1 count43 (:18)
- ?? - ? ? DFFE 1 3 0 2 count42 (:19)
- ?? - ? ? DFFE 1 2 0 2 count41 (:20)
- ?? - ? ? DFFE 1 1 0 3 count40 (:21)
- ?? - ? ? AND2 0 2 0 16 :27
- ?? - ? ? DFFE 1 3 0 2 count1110 (:82)
- ?? - ? ? DFFE 1 3 0 3 count119 (:83)
- ?? - ? ? DFFE 1 3 0 2 count118 (:84)
- ?? - ? ? DFFE 1 3 0 1 count117 (:85)
- ?? - ? ? DFFE 1 3 0 1 count116 (:86)
- ?? - ? ? DFFE 1 3 0 1 count115 (:87)
- ?? - ? ? DFFE 1 3 0 1 count114 (:88)
- ?? - ? ? DFFE 1 3 0 1 count113 (:89)
- ?? - ? ? DFFE 1 3 0 1 count112 (:90)
- ?? - ? ? DFFE 1 3 0 1 count111 (:91)
- ?? - ? ? DFFE 1 2 0 2 count110 (:92)
- ?? - ? ? AND2 0 3 0 10 :107
- ?? - ? ? DFFE 0 1 0 1 count2 (:284)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\0305632tyx\speaker.rpt
speaker
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 6/16( 37%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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