📄 liushuideng.rpt
字号:
- 1 - C 09 OR2 ! 0 3 1 0 :268
- 4 - C 09 OR2 ! 0 3 1 0 :278
- 6 - C 08 OR2 0 3 1 0 :368
- 5 - C 08 OR2 0 3 1 0 :392
- 3 - C 08 OR2 0 3 1 0 :416
- 1 - C 08 OR2 0 3 1 0 :449
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\0306407yyw\liushuideng.rpt
liushuideng
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\0306407yyw\liushuideng.rpt
liushuideng
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 CLK
Device-Specific Information: e:\0306407yyw\liushuideng.rpt
liushuideng
** EQUATIONS **
CLK : INPUT;
-- Node name is ':12' = 'indata0'
-- Equation name is 'indata0', location is LC8_C8, type is buried.
indata0 = DFFE(!indata0, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':11' = 'indata1'
-- Equation name is 'indata1', location is LC7_C8, type is buried.
indata1 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = indata0 & !indata1
# !indata0 & indata1;
-- Node name is ':10' = 'indata2'
-- Equation name is 'indata2', location is LC2_C8, type is buried.
indata2 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = !indata0 & indata2
# !indata1 & indata2
# indata0 & indata1 & !indata2;
-- Node name is 'T0'
-- Equation name is 'T0', type is output
T0 = _LC1_C8;
-- Node name is 'T1'
-- Equation name is 'T1', type is output
T1 = _LC3_C8;
-- Node name is 'T2'
-- Equation name is 'T2', type is output
T2 = _LC5_C8;
-- Node name is 'T3'
-- Equation name is 'T3', type is output
T3 = _LC6_C8;
-- Node name is 'T4'
-- Equation name is 'T4', type is output
T4 = !_LC2_C6;
-- Node name is 'T5'
-- Equation name is 'T5', type is output
T5 = !_LC4_C8;
-- Node name is 'T6'
-- Equation name is 'T6', type is output
T6 = !_LC1_C9;
-- Node name is 'T7'
-- Equation name is 'T7', type is output
T7 = !_LC4_C9;
-- Node name is ':248'
-- Equation name is '_LC2_C6', type is buried
!_LC2_C6 = _LC2_C6~NOT;
_LC2_C6~NOT = LCELL( _EQ003);
_EQ003 = !indata0
# !indata1
# indata2;
-- Node name is ':258'
-- Equation name is '_LC4_C8', type is buried
!_LC4_C8 = _LC4_C8~NOT;
_LC4_C8~NOT = LCELL( _EQ004);
_EQ004 = indata0
# !indata1
# indata2;
-- Node name is ':268'
-- Equation name is '_LC1_C9', type is buried
!_LC1_C9 = _LC1_C9~NOT;
_LC1_C9~NOT = LCELL( _EQ005);
_EQ005 = !indata0
# indata1
# indata2;
-- Node name is ':278'
-- Equation name is '_LC4_C9', type is buried
!_LC4_C9 = _LC4_C9~NOT;
_LC4_C9~NOT = LCELL( _EQ006);
_EQ006 = indata0
# indata1
# indata2;
-- Node name is ':368'
-- Equation name is '_LC6_C8', type is buried
_LC6_C8 = LCELL( _EQ007);
_EQ007 = indata0
# indata1
# !indata2;
-- Node name is ':392'
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = LCELL( _EQ008);
_EQ008 = !indata0
# indata1
# !indata2;
-- Node name is ':416'
-- Equation name is '_LC3_C8', type is buried
_LC3_C8 = LCELL( _EQ009);
_EQ009 = indata0
# !indata1
# !indata2;
-- Node name is ':449'
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = LCELL( _EQ010);
_EQ010 = !indata1 & indata2
# !indata0 & indata2
# indata1 & !indata2
# !indata0 & !indata1
# indata0 & !indata2;
Project Information e:\0306407yyw\liushuideng.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,925K
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