speaker.vhd

来自「可以轻松实现秒表计数流水灯计数功能控制器」· VHDL 代码 · 共 51 行

library ieee;
use ieee.std_logic_1164.all;

entity speaker is
port( 
     clk  : in std_logic;
     tone : in integer range 0 to 16#7ff#;   --"2047";
     spks : out std_logic);
end speaker;

architecture behav of speaker is
signal preclk : std_logic;
signal fullspks : std_logic;
begin
divideclk: process(clk)
variable count4 : integer range 0 to 15;
begin
preclk<='0';
if count4>11 then
preclk<='1';
count4:=0;
elsif clk'event and clk='1' then
count4:=count4+1;
end if;
end process;
genspks : process(preclk,tone)     --"preclk=1MHZ";
variable count11 : integer range 0 to 16#7ff#;   --"2047";
begin
if preclk'event and preclk='1' then
if count11=16#7ff# then   --b"111,1111,1111";
count11:=tone;
fullspks<='1';
else count11:=count11+1;
fullspks<='0';
end if;
end if;
end process;
delay: process(fullspks)     --"fullspks=488.2815HZ";
variable count2 : std_logic;
begin
if fullspks'event and fullspks='1' then
count2:=not count2;
if count2='1' then
spks<='1';
else
spks<='0';                  --"spks=244.14075HZ";
end if;
end if;
end process;
end behav;