📄 speaker.rpt
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Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\0306407yyw\yinyue\speaker.rpt
speaker
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 16 :27
INPUT 4 clk
DFF 2 fullspks
Device-Specific Information: e:\0306407yyw\yinyue\speaker.rpt
speaker
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 16 :27
Device-Specific Information: e:\0306407yyw\yinyue\speaker.rpt
speaker
** EQUATIONS **
clk : INPUT;
tone0 : INPUT;
tone1 : INPUT;
tone2 : INPUT;
tone3 : INPUT;
tone4 : INPUT;
tone5 : INPUT;
tone6 : INPUT;
tone7 : INPUT;
tone8 : INPUT;
tone9 : INPUT;
tone10 : INPUT;
-- Node name is ':284' = 'count2'
-- Equation name is 'count2', location is LC1_A7, type is buried.
count2 = DFFE(!count2, fullspks, VCC, VCC, VCC);
-- Node name is ':21' = 'count40'
-- Equation name is 'count40', location is LC1_A6, type is buried.
count40 = DFFE(!count40, GLOBAL( clk), !_LC8_A10, VCC, VCC);
-- Node name is ':20' = 'count41'
-- Equation name is 'count41', location is LC2_A10, type is buried.
count41 = DFFE( _EQ001, GLOBAL( clk), !_LC8_A10, VCC, VCC);
_EQ001 = count40 & !count41
# !count40 & count41;
-- Node name is ':19' = 'count42'
-- Equation name is 'count42', location is LC6_A10, type is buried.
count42 = DFFE( _EQ002, GLOBAL( clk), !_LC8_A10, VCC, VCC);
_EQ002 = !count40 & count42
# !count41 & count42
# count40 & count41 & !count42;
-- Node name is ':18' = 'count43'
-- Equation name is 'count43', location is LC5_A10, type is buried.
count43 = DFFE( _EQ003, GLOBAL( clk), !_LC8_A10, VCC, VCC);
_EQ003 = !count42 & count43
# !count40 & count43
# !count41 & count43
# count40 & count41 & count42 & !count43;
-- Node name is ':92' = 'count110'
-- Equation name is 'count110', location is LC5_A9, type is buried.
count110 = DFFE( _EQ004, _LC8_A10, VCC, VCC, VCC);
_EQ004 = !count110
# _LC1_A1 & tone0;
-- Node name is ':91' = 'count111'
-- Equation name is 'count111', location is LC4_A9, type is buried.
count111 = DFFE( _EQ005, _LC8_A10, VCC, VCC, VCC);
_EQ005 = count110 & !count111 & !_LC1_A1
# !count110 & count111 & !_LC1_A1
# _LC1_A1 & tone1;
-- Node name is ':90' = 'count112'
-- Equation name is 'count112', location is LC6_A9, type is buried.
count112 = DFFE( _EQ006, _LC8_A10, VCC, VCC, VCC);
_EQ006 = count112 & !_LC1_A1 & !_LC1_A9
# !count112 & !_LC1_A1 & _LC1_A9
# _LC1_A1 & tone2;
-- Node name is ':89' = 'count113'
-- Equation name is 'count113', location is LC7_A9, type is buried.
count113 = DFFE( _EQ007, _LC8_A10, VCC, VCC, VCC);
_EQ007 = count113 & !_LC1_A1 & !_LC3_A9
# !count113 & !_LC1_A1 & _LC3_A9
# _LC1_A1 & tone3;
-- Node name is ':88' = 'count114'
-- Equation name is 'count114', location is LC1_A5, type is buried.
count114 = DFFE( _EQ008, _LC8_A10, VCC, VCC, VCC);
_EQ008 = count114 & !_LC1_A1 & !_LC2_A9
# !count114 & !_LC1_A1 & _LC2_A9
# _LC1_A1 & tone4;
-- Node name is ':87' = 'count115'
-- Equation name is 'count115', location is LC3_A10, type is buried.
count115 = DFFE( _EQ009, _LC8_A10, VCC, VCC, VCC);
_EQ009 = count115 & !_LC1_A1 & !_LC2_A5
# !count115 & !_LC1_A1 & _LC2_A5
# _LC1_A1 & tone5;
-- Node name is ':86' = 'count116'
-- Equation name is 'count116', location is LC4_A10, type is buried.
count116 = DFFE( _EQ010, _LC8_A10, VCC, VCC, VCC);
_EQ010 = count116 & !_LC1_A1 & !_LC1_A10
# !count116 & !_LC1_A1 & _LC1_A10
# _LC1_A1 & tone6;
-- Node name is ':85' = 'count117'
-- Equation name is 'count117', location is LC4_A1, type is buried.
count117 = DFFE( _EQ011, _LC8_A10, VCC, VCC, VCC);
_EQ011 = count117 & !_LC1_A1 & !_LC7_A10
# !count117 & !_LC1_A1 & _LC7_A10
# _LC1_A1 & tone7;
-- Node name is ':84' = 'count118'
-- Equation name is 'count118', location is LC5_A1, type is buried.
count118 = DFFE( _EQ012, _LC8_A10, VCC, VCC, VCC);
_EQ012 = count118 & !_LC1_A1 & !_LC2_A1
# !count118 & !_LC1_A1 & _LC2_A1
# _LC1_A1 & tone8;
-- Node name is ':83' = 'count119'
-- Equation name is 'count119', location is LC7_A1, type is buried.
count119 = DFFE( _EQ013, _LC8_A10, VCC, VCC, VCC);
_EQ013 = count119 & !_LC1_A1 & !_LC3_A1
# !count119 & !_LC1_A1 & _LC3_A1
# _LC1_A1 & tone9;
-- Node name is ':82' = 'count1110'
-- Equation name is 'count1110', location is LC8_A1, type is buried.
count1110 = DFFE( _EQ014, _LC8_A10, VCC, VCC, VCC);
_EQ014 = !count119 & count1110
# count1110 & !_LC3_A1
# count119 & !count1110 & _LC3_A1
# count1110 & tone10;
-- Node name is ':16' = 'fullspks'
-- Equation name is 'fullspks', location is LC6_A1, type is buried.
fullspks = DFFE( _EQ015, _LC8_A10, VCC, VCC, VCC);
_EQ015 = count118 & count119 & count1110 & _LC2_A1;
-- Node name is 'spks'
-- Equation name is 'spks', type is output
spks = _LC7_A7;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = LCELL( _EQ016);
_EQ016 = count110 & count111;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A9', type is buried
_LC3_A9 = LCELL( _EQ017);
_EQ017 = count112 & _LC1_A9;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A9', type is buried
_LC2_A9 = LCELL( _EQ018);
_EQ018 = count113 & _LC3_A9;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = LCELL( _EQ019);
_EQ019 = count114 & _LC2_A9;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = LCELL( _EQ020);
_EQ020 = count115 & _LC2_A5;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A10', type is buried
_LC7_A10 = LCELL( _EQ021);
_EQ021 = count116 & _LC1_A10;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ022);
_EQ022 = count117 & _LC7_A10;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ023);
_EQ023 = count118 & _LC2_A1;
-- Node name is ':13'
-- Equation name is '_LC7_A7', type is buried
_LC7_A7 = DFFE(!count2, fullspks, VCC, VCC, VCC);
-- Node name is ':27'
-- Equation name is '_LC8_A10', type is buried
_LC8_A10 = LCELL( _EQ024);
_EQ024 = count42 & count43;
-- Node name is ':107'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ025);
_EQ025 = count119 & count1110 & _LC3_A1;
Project Information e:\0306407yyw\yinyue\speaker.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,992K
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