tonetaba.rpt

可以轻松实现秒表计数流水灯计数功能控制器

_LC4_B10 = LCELL( _EQ030);
  _EQ030 = !_LC1_B12 &  _LC2_B10 &  _LC3_B10;

-- Node name is ':979' 
-- Equation name is '_LC2_B10', type is buried 
_LC2_B10 = LCELL( _EQ031);
  _EQ031 =  _LC4_B10 &  _LC5_B10
         #  _LC5_B10 &  _LC8_B6
         #  _LC1_B6;

-- Node name is ':1005' 
-- Equation name is '_LC5_B4', type is buried 
_LC5_B4  = LCELL( _EQ032);
  _EQ032 =  _LC1_B4 & !_LC2_B4 &  _LC6_B4
         #  _LC1_B4 &  _LC7_B6;

-- Node name is '~1017~1' 
-- Equation name is '~1017~1', location is LC2_B3, type is buried.
-- synthesized logic cell 
_LC2_B3  = LCELL( _EQ033);
  _EQ033 = !_LC5_B1 & !_LC8_B6;

-- Node name is ':1017' 
-- Equation name is '_LC2_B11', type is buried 
_LC2_B11 = LCELL( _EQ034);
  _EQ034 =  _LC2_B3 & !_LC3_B1 &  _LC5_B4
         #  _LC2_B3 & !_LC3_B1 &  _LC4_B1;

-- Node name is ':1021' 
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = LCELL( _EQ035);
  _EQ035 = !_LC1_B1 &  _LC2_B11
         # !_LC1_B1 &  _LC2_B6
         #  _LC1_B6;

-- Node name is ':1039' 
-- Equation name is '_LC7_B12', type is buried 
_LC7_B12 = LCELL( _EQ036);
  _EQ036 = !_LC1_B12 &  _LC6_B12
         #  _LC3_B6;

-- Node name is '~1054~1' 
-- Equation name is '~1054~1', location is LC8_B12, type is buried.
-- synthesized logic cell 
_LC8_B12 = LCELL( _EQ037);
  _EQ037 =  _LC8_B6
         # !_LC6_B1
         # !_LC4_B6 &  _LC7_B12;

-- Node name is ':1063' 
-- Equation name is '_LC6_B12', type is buried 
_LC6_B12 = LCELL( _EQ038);
  _EQ038 =  _LC4_B12 &  _LC8_B12
         #  _LC4_B12 &  _LC5_B1
         #  _LC1_B6;

-- Node name is ':1078' 
-- Equation name is '_LC3_B11', type is buried 
_LC3_B11 = LCELL( _EQ039);
  _EQ039 = !_LC5_B6 &  _LC6_B11
         #  _LC4_B2
         #  _LC6_B6;

-- Node name is ':1095' 
-- Equation name is '_LC4_B11', type is buried 
_LC4_B11 = LCELL( _EQ040);
  _EQ040 =  _LC1_B8 & !_LC3_B1 &  _LC3_B11
         # !_LC3_B1 &  _LC4_B1;

-- Node name is ':1105' 
-- Equation name is '_LC6_B11', type is buried 
_LC6_B11 = LCELL( _EQ041);
  _EQ041 = !_LC2_B6 &  _LC4_B11
         # !_LC2_B3 & !_LC2_B6
         #  _LC7_B4;

-- Node name is ':1128' 
-- Equation name is '_LC2_B12', type is buried 
_LC2_B12 = LCELL( _EQ042);
  _EQ042 = !_LC2_B4 & !_LC3_B6 &  _LC5_B12
         # !_LC3_B6 &  _LC4_B2;

-- Node name is ':1132' 
-- Equation name is '_LC3_B12', type is buried 
_LC3_B12 = LCELL( _EQ043);
  _EQ043 =  _LC2_B12 & !_LC4_B1
         # !_LC4_B1 &  _LC4_B6
         #  _LC3_B1;

-- Node name is ':1147' 
-- Equation name is '_LC5_B12', type is buried 
_LC5_B12 = LCELL( _EQ044);
  _EQ044 =  _LC2_B3 &  _LC3_B12 &  _LC4_B12
         #  _LC1_B6;

-- Node name is '~1149~1' 
-- Equation name is '~1149~1', location is LC4_B12, type is buried.
-- synthesized logic cell 
_LC4_B12 = LCELL( _EQ045);
  _EQ045 = !_LC1_B1 & !_LC2_B6;

-- Node name is '~1179~1' 
-- Equation name is '~1179~1', location is LC3_B10, type is buried.
-- synthesized logic cell 
_LC3_B10 = LCELL( _EQ046);
  _EQ046 =  _LC1_B8 &  _LC6_B1;

-- Node name is ':1179' 
-- Equation name is '_LC5_B3', type is buried 
_LC5_B3  = LCELL( _EQ047);
  _EQ047 = !_LC1_B12 &  _LC3_B10 &  _LC8_B3;

-- Node name is '~1188~1' 
-- Equation name is '~1188~1', location is LC4_B3, type is buried.
-- synthesized logic cell 
_LC4_B3  = LCELL( _EQ048);
  _EQ048 = !_LC2_B6 & !_LC5_B1;

-- Node name is '~1189~1' 
-- Equation name is '~1189~1', location is LC7_B4, type is buried.
-- synthesized logic cell 
_LC7_B4  = LCELL( _EQ049);
  _EQ049 =  _LC1_B6
         #  _LC1_B1;

-- Node name is ':1189' 
-- Equation name is '_LC8_B3', type is buried 
_LC8_B3  = LCELL( _EQ050);
  _EQ050 =  _LC7_B4
         #  _LC4_B3 &  _LC8_B6
         #  _LC4_B3 &  _LC5_B3;

-- Node name is ':1231' 
-- Equation name is '_LC6_B10', type is buried 
_LC6_B10 = LCELL( _EQ051);
  _EQ051 = !_LC1_B6 &  _LC5_B10 &  _LC6_B10 & !_LC7_B10;

-- Node name is '~1233~1' 
-- Equation name is '~1233~1', location is LC6_B1, type is buried.
-- synthesized logic cell 
_LC6_B1  = LCELL( _EQ052);
  _EQ052 = !_LC3_B1 & !_LC4_B1;

-- Node name is '~1233~2' 
-- Equation name is '~1233~2', location is LC5_B10, type is buried.
-- synthesized logic cell 
_LC5_B10 = LCELL( _EQ053);
  _EQ053 = !_LC1_B1 &  _LC4_B3;

-- Node name is ':1243' 
-- Equation name is '_LC3_B4', type is buried 
_LC3_B4  = LCELL( _EQ054);
  _EQ054 =  _LC4_B4 & !_LC5_B6
         #  _LC7_B6
         #  _LC6_B6;

-- Node name is '~1257~1' 
-- Equation name is '~1257~1', location is LC1_B8, type is buried.
-- synthesized logic cell 
_LC1_B8  = LCELL( _EQ055);
  _EQ055 = !_LC3_B6 & !_LC4_B6;

-- Node name is '~1257~2' 
-- Equation name is '~1257~2', location is LC1_B4, type is buried.
-- synthesized logic cell 
_LC1_B4  = LCELL( _EQ056);
  _EQ056 = !_LC1_B2 &  _LC1_B8;

-- Node name is ':1261' 
-- Equation name is '_LC8_B4', type is buried 
_LC8_B4  = LCELL( _EQ057);
  _EQ057 =  _LC1_B4 &  _LC3_B4
         #  _LC8_B6
         # !_LC6_B1;

-- Node name is ':1273' 
-- Equation name is '_LC4_B4', type is buried 
_LC4_B4  = LCELL( _EQ058);
  _EQ058 = !_LC2_B6 & !_LC5_B1 & !_LC7_B4 &  _LC8_B4;

-- Node name is ':1282' 
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = LCELL( _EQ059);
  _EQ059 =  _LC4_B5 & !_LC5_B6
         #  _LC6_B6;

-- Node name is ':1291' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ060);
  _EQ060 =  _LC6_B5 & !_LC7_B6
         #  _LC1_B2
         #  _LC3_B6;

-- Node name is ':1300' 
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = LCELL( _EQ061);
  _EQ061 = !_LC4_B6 &  _LC7_B5
         # !_LC6_B1;

-- Node name is ':1315' 
-- Equation name is '_LC4_B5', type is buried 
_LC4_B5  = LCELL( _EQ062);
  _EQ062 = !_LC7_B4 &  _LC8_B5 & !_LC8_B6
         # !_LC4_B3 & !_LC7_B4;

-- Node name is '~1330~1' 
-- Equation name is '~1330~1', location is LC4_B2, type is buried.
-- synthesized logic cell 
!_LC4_B2 = _LC4_B2~NOT;
_LC4_B2~NOT = LCELL( _EQ063);
  _EQ063 = !_LC1_B2 & !_LC7_B6;

-- Node name is ':1330' 
-- Equation name is '_LC5_B11', type is buried 
_LC5_B11 = LCELL( _EQ064);
  _EQ064 =  _LC1_B11 & !_LC6_B6
         #  _LC5_B6 & !_LC6_B6
         #  _LC4_B2;

-- Node name is ':1339' 
-- Equation name is '_LC7_B11', type is buried 
_LC7_B11 = LCELL( _EQ065);
  _EQ065 = !_LC3_B6 &  _LC5_B11
         #  _LC4_B1
         #  _LC4_B6;

-- Node name is ':1348' 
-- Equation name is '_LC8_B11', type is buried 
_LC8_B11 = LCELL( _EQ066);
  _EQ066 = !_LC3_B1 &  _LC7_B11
         #  _LC5_B1
         #  _LC8_B6;

-- Node name is ':1357' 
-- Equation name is '_LC1_B11', type is buried 
_LC1_B11 = LCELL( _EQ067);
  _EQ067 = !_LC1_B6 & !_LC2_B6 &  _LC8_B11
         #  _LC1_B1 & !_LC1_B6;



Project Information                          e:\0306407yyw\yinyue\tonetaba.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,380K