📄 ax88170.h
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//*++
//
//Copyright (c) 1999-2002 ASIX Electronics Corporation
//
//Module Name:
// ax88170.h
//
//Abstract:
// The main header for an ASIX AX88172 Miniport driver.
//
//Author:
// William Lee, November 1999, July 2002,
//
//Environment:
// Architecturally, there is an assumption in this driver
// that we are on a little endian machine.
//
//Notes:
// optional-notes
//
//Revision History:
//
//--*
#include <ndis.h>
#define AX88172_NDIS_MAJOR_VERSION 5
#define AX88172_NDIS_MINOR_VERSION 0
#define MiiPhyCtrlReset ((USHORT) 0x8000)
#define MiiPhyCtrlLoopBack ((USHORT) 0x4000)
#define MiiPhyCtrlSpeed100 ((USHORT) 0x2000)
#define MiiPhyCtrlEnableNway ((USHORT) 0x1000)
#define MiiPhyCtrlPowerDown ((USHORT) 0x0800)
#define MiiPhyCtrlIsolate ((USHORT) 0x0400)
#define MiiPhyCtrlRestartNway ((USHORT) 0x0200)
#define MiiPhyCtrlDuplexMode ((USHORT) 0x0100)
#define MiiPhyCtrlCollisionTest ((USHORT) 0x0080)
#define MiiPhyCtrlReservedBitsMask ((USHORT) 0x007F)
#define MiiPhyCtrlForce10 ((USHORT) 0xCEFF)
#define MiiPhy100BaseT4 ((USHORT) 0x8000)
#define MiiPhy100BaseTxFD ((USHORT) 0x4000)
#define MiiPhy100BaseTx ((USHORT) 0x2000)
#define MiiPhy10BaseTFD ((USHORT) 0x1000)
#define MiiPhy10BaseT ((USHORT) 0x0800)
#define MiiPhyStatReservedBitsMask ((USHORT) 0x07C0)
#define MiiPhyNwayPauseEnable ((USHORT) 0x0400)
#define MiiPhyNwayComplete ((USHORT) 0x0020)
#define MiiPhyRemoteFault ((USHORT) 0x0010)
#define MiiPhyNwayCapable ((USHORT) 0x0008)
#define MiiPhyLinkStatus ((USHORT) 0x0004)
#define MiiPhyJabberDetect ((USHORT) 0x0002)
#define MiiPhyExtendedCapabilities ((USHORT) 0x0001)
#define MiiPhyNwayNextPageAble ((USHORT) 0x8000)
#define MiiPhyNwayACK ((USHORT) 0x4000)
#define MiiPhyNwayRemoteFault ((USHORT) 0x2000)
#define MiiPhyNwayReservedBitsMask ((USHORT) 0x1C00)
#define MiiPhyNway100BaseT4 ((USHORT) 0x0200)
#define MiiPhyNway100BaseTxFD ((USHORT) 0x0100)
#define MiiPhyNway100BaseTx ((USHORT) 0x0080)
#define MiiPhyNway10BaseTFD ((USHORT) 0x0040)
#define MiiPhyNway10BaseT ((USHORT) 0x0020)
#define MiiPhyNwaySelectorMask ((USHORT) 0x001F)
#define MiiPhyStat100BaseTxFD MiiPhyNway100BaseTxFD
#define MiiPhyStat100BaseTx MiiPhyNway100BaseTx
#define MiiPhyStat10BaseTxFD MiiPhyNway10BaseTFD
#define MiiPhyStat10BaseTx MiiPhyNway10BaseT
#define MiiPhyNwayExpReservedBitsMask ((USHORT) 0xFFE0)
#define MiiPhyNwayExpMultipleLinkFault ((USHORT) 0x0010)
#define MiiPhyNwayExpLinkPartnerNextPageAble ((USHORT) 0x0008)
#define MiiPhyNwayExpNextPageAble ((USHORT) 0x0004)
#define MiiPhyNwayExpReceivedLinkCodePage ((USHORT) 0x0002)
#define MiiPhyNwayExpLinkPartnerNwayAble ((USHORT) 0x0001)
// MII PHY Register's
#define PhyControlReg 0
#define PhyStatusReg 1
#define PhyId_1 2
#define PhyId_2 3
#define PhyNwayAdvertisement 4
#define PhyNwayLinkPartnerAbility 5
#define PhyNwayExpansion 6
#define PhyNwayNextPageTransmit 7
#define PhyAddress 8
#define PhyReserved 9 // ..15 are PHY's reserved
#define PhyVendorSpecific 16 // 16-31 are Vendor's Specific
#define NatPhyParRegister 25
//!!! bit 0..3 (PHY revision) should be ignored and reset!!!
#define TIE2101_0 0x40005030 //TI TNETE2101
#define BCM5000_0 0x03E00000 //Broadcom
#define DP83840_0 0x20005C00 //National
#define DP83846_0 0x20005C20 //National
#define DP83851_0 DP83846_0 //National HomePHY
#define ICS1890_0 0x0015f420 //ICS
#define QSI6612_0 0x01814400 //QSI
#define LUC6612_0 0x018074C0 //Lucent
#define LU3X31T_0 0x00437410 //Lucent 3x31T
#define AX88790_0 0x00887900 //AX88790
#define MTD972_0 0x00000000 //MYSON
#define MTD972_1 0x0302D000 //MYSON
#define DM9101_0 0x0181B800 //DaviCom
#define LXT970_0 0x78100000 //Level One
#define AH101_0 0x00225510 //TRex
#define AM79C901_0 0x00006B70 //AMD 10Base-T
#define AM79C901_1 0x00006B90 //AMD HomePHY
#define RTL8201_0 0x00008200 //Realtek RTL8201BL
#define GENERIC_PHY 0xFFFFFFFF
USHORT
_MiiReadRegister(
IN NDIS_HANDLE MiniportAdapterContext,
IN USHORT uRegNum
);
VOID
_MiiWriteRegister(
IN NDIS_HANDLE MiniportAdapterContext,
IN USHORT uRegNum,
IN USHORT uRegData
);
#include <usbdi.h>
#include <usbdlib.h>
#pragma pack(1)
#define STATIC static
//
// USB definitions
#define VendorId 0x0b95 //ASIX Electronics Corp.
#define ProductId 0x1720
#define AcceptedUSBDIVersion 0x0101
#define AcceptedUSBVersion 0x0100
#define numTransmitQ 8 //CAN'T LESS THAN 2
#define numReceiveQ 16 //CAN'T LESS THAN 4
#define InterruptBufferSize 16
#define HaltTransmit 1
#define HaltReceive 2
#define HaltInterrupt 4
//
// Size of the ethernet header
//
#define ETH_HEADER_SIZE 14
//
// Size of the ethernet address
//
#define AX88172_LENGTH_OF_ADDRESS 6
//
// Number of bytes allowed in a lookahead (max)
//
#define AX88172_MAX_LOOKAHEAD (1514 - ETH_HEADER_SIZE)
#define PACKET_TYPE_PROMISCUOUS 1
#define PACKET_TYPE_ALL_MULTICAST 2
#define PACKET_TYPE_DIRECTED 4
#define PACKET_TYPE_BROADCAST 8
#define PACKET_TYPE_MULTICAST 0x10
//
#define OID_BACKDOOR_RESERVED 0xFF010200
#define OID_BACKDOOR_OPEN 0xFF010201
#define OID_BACKDOOR_CLOSE 0xFF010202
#define OID_BACKDOOR_INPORT 0xFF010203
#define OID_BACKDOOR_OUTPORT 0xFF010204
#define OID_BACKDOOR_RECEIVE 0xFF010205
#define OID_BACKDOOR_TRANSMIT 0xFF010206
#define OID_BACKDOOR_GPBITS 0xFF010207
//
//
// This structure contains information about the driver
// itself. There is only have one of these structures.
//
typedef struct _DRIVER_BLOCK
{
//
// NDIS wrapper information.
NDIS_HANDLE NdisWrapperHandle; // returned from NdisInitializeWrapper
//
// Adapters registered for this Miniport driver.
NDIS_HANDLE AdapterQueue;
} DRIVER_BLOCK, * PDRIVER_BLOCK;
// used to track driver-generated io irps for staged read/write processing
typedef struct _BULKUSB_RW_CONTEXT
{
struct _AX_ADAPTER *Adapter;
PIRP irp;
PURB pUrb;
} BULKUSB_RW_CONTEXT, *PBULKUSB_RW_CONTEXT;
//
// This structure contains all the information about a single
// adapter that this driver is controlling.
//
typedef struct _AX_ADAPTER
{
//
// used by DriverBlock->AdapterQueue
struct _AX_ADAPTER * NextAdapter;
//
// This is the handle given by the wrapper for calling ndis functions.
NDIS_HANDLE MiniportAdapterHandle;
NDIS_MINIPORT_TIMER InterruptTimer;
NDIS_MINIPORT_TIMER ReceiveTimer;
NDIS_MINIPORT_TIMER TransmitTimer;
NDIS_MINIPORT_TIMER ReceiveHandleTimer;
NDIS_MINIPORT_TIMER TransmitHandleTimer;
NDIS_SPIN_LOCK TransmitSpinLock;
NDIS_SPIN_LOCK ReceiveIoCountSpinLock;
NDIS_SPIN_LOCK TransmitIoCountSpinLock;
BOOLEAN fgReady;
BOOLEAN fgBusy;
BOOLEAN fgMediaLinkUp;
BOOLEAN FixedPhy;
BOOLEAN FlowControl;
BOOLEAN StopReceive;
BOOLEAN StartReceive;
BOOLEAN StartTransmit;
BOOLEAN PhoneNetworkMedia;
BOOLEAN PrimaryPhyExist;
BOOLEAN SecondaryPhyExist;
BOOLEAN PrimaryPhyType;
BOOLEAN SecondaryPhyType;
PDEVICE_OBJECT PhysicalDeviceObject;
ULONG TransmitIoCount;
ULONG ReceiveIoCount;
BULKUSB_RW_CONTEXT PendingInterrupt;
BULKUSB_RW_CONTEXT PendingTransmit;
BULKUSB_RW_CONTEXT PendingReceive;
PUSB_CONFIGURATION_DESCRIPTOR UsbConfigurationDescriptor;
USBD_CONFIGURATION_HANDLE UsbConfigurationHandle;
USBD_PIPE_HANDLE InterruptPipe;
USBD_PIPE_HANDLE TransmitPipe;
USBD_PIPE_HANDLE ReceivePipe;
ULONG ulPrimaryPhyId;
ULONG ulSecondaryPhyId;
USHORT PrimaryPhy;
USHORT SecondaryPhy;
USHORT uPartnerAbility;
USHORT uRemoteWakeup;
USHORT uPhoneLine;
USHORT GPIO;
UINT MaximumPacketSize;
//
// Configuration information
//
//
// Number of buffer in this adapter.
UINT NumQueuePackets;
//
// Type of PHY connection type.
UINT uConnectionType;
//
// Transmit information.
//
//
// The first/last of the pending transmit queue.
PNDIS_PACKET FirstPacket;
PNDIS_PACKET LastPacket;
UINT FirstTransmit;
UINT LastTransmit;
//
// Receive information
//
//
// The first/last of the pending receive.
UINT FirstReceive;
UINT LastReceive;
//
// Operational information.
//
//
// The ethernet address currently in use.
UCHAR StationAddress[AX88172_LENGTH_OF_ADDRESS];
//
// The ethernet address that is burned into the adapter.
UCHAR PermanentAddress[AX88172_LENGTH_OF_ADDRESS];
//
// The current packet filter in use.
ULONG PacketFilterSave;
UCHAR mcFilter[8];
//
// The lookahead buffer size in use.
ULONG MaxLookAhead;
//
// Reset information.
USHORT PacketFilter; // contents of NIC RCR
UCHAR HaltEvents;
UCHAR ChipVersion;
//
// Buffers and Statistics used by Set/QueryInformation.
UINT ReceiveLength[numReceiveQ];
UINT TransmitLength[numTransmitQ];
PUCHAR ReceiveBuffer[numReceiveQ];
PUCHAR TransmitBuffer[numTransmitQ];
ULONG MissedPackets;
ULONG FramesXmitBad;
UCHAR InterruptBuffer[InterruptBufferSize];
ULONG FramesRcvGood;
ULONG FramesXmitGood;
} AX_ADAPTER, * PAX_ADAPTER;
//
// Generic test for cancel condition.
//
#define USBD_CANCEL(Status) ((ULONG)((Status)&(USBD_STATUS_CANCELING|USBD_STATUS_CANCELED)))
//
// Given a MiniportContextHandle return the PAX_ADAPTER it represents.
//
#define PAX_ADAPTER_FROM_CONTEXT_HANDLE(Handle) \
((PAX_ADAPTER)(Handle))
//
// Given a pointer to a AX_ADAPTER return the proper MiniportContextHandle.
//
#define CONTEXT_HANDLE_FROM_PAX_ADAPTER(Ptr) \
((NDIS_HANDLE)(Ptr))
//
// Macros to extract high and low bytes of a word.
//
#define MSB(Value) ((UCHAR)((((ULONG)Value) >> 8) & 0xff))
#define LSB(Value) ((UCHAR)(((ULONG)Value) & 0xff))
//
// What we map into the reserved section of a packet.
// Cannot be more than 8 bytes (see ASSERT in ax88172.c).
//
typedef struct _MINIPORT_RESERVED
{
PNDIS_PACKET Next; // used to link in the queues (4 bytes)
UINT TotalPacketLength;
} MINIPORT_RESERVED, * PMINIPORT_RESERVED;
//
// Retrieve the MINIPORT_RESERVED structure from a packet.
//
#define RESERVED(Packet) ((PMINIPORT_RESERVED)((Packet)->MiniportReserved))
//
// Declarations for functions in ax88172.c.
//
NDIS_STATUS
AX88172SetInformation(
IN NDIS_HANDLE MiniportAdapterContext,
IN NDIS_OID Oid,
IN PVOID InformationBuffer,
IN ULONG InformationBufferLength,
OUT PULONG BytesRead,
OUT PULONG BytesNeeded
);
VOID
AX88172Halt(
IN NDIS_HANDLE MiniportAdapterContext
);
NDIS_STATUS
AX88172RegisterAdapter(
IN PAX_ADAPTER Adapter
);
NDIS_STATUS
AX88172Initialize(
OUT PNDIS_STATUS OpenErrorStatus,
OUT PUINT SelectedMediumIndex,
IN PNDIS_MEDIUM MediumArray,
IN UINT MediumArraySize,
IN NDIS_HANDLE MiniportAdapterHandle,
IN NDIS_HANDLE ConfigurationHandle
);
NDIS_STATUS
AX88172TransferData(
OUT PNDIS_PACKET Packet,
OUT PUINT BytesTransferred,
IN NDIS_HANDLE MiniportAdapterContext,
IN NDIS_HANDLE MiniportReceiveContext,
IN UINT ByteOffset,
IN UINT BytesToTransfer
);
NDIS_STATUS
AX88172Send(
IN NDIS_HANDLE MiniportAdapterContext,
IN PNDIS_PACKET Packet,
IN UINT Flags
);
NDIS_STATUS
AX88172Reset(
OUT PBOOLEAN AddressingReset,
IN NDIS_HANDLE MiniportAdapterContext
);
NDIS_STATUS
AX88172QueryInformation(
IN NDIS_HANDLE MiniportAdapterContext,
IN NDIS_OID Oid,
IN PVOID InformationBuffer,
IN ULONG InformationBufferLength,
OUT PULONG BytesWritten,
OUT PULONG BytesNeeded
);
BOOLEAN
AXCheckForHang(
IN NDIS_HANDLE MiniportAdapterContext
);
VOID
MiiReadRegister(
IN PAX_ADAPTER Adapter,
IN PURB pUrb,
IN USHORT uPhyAddr,
IN USHORT uRegNum,
IN PUSHORT puRegData
);
VOID
MiiWriteRegister(
IN PAX_ADAPTER Adapter,
IN PURB pUrb,
IN USHORT uPhyAddr,
IN USHORT uRegNum,
IN USHORT uRegData
);
VOID
CardStart(
IN PAX_ADAPTER Adapter
);
VOID
CardStop(
IN PAX_ADAPTER Adapter
);
VOID
AX88172DoNextSend(
PAX_ADAPTER Adapter
);
VOID
BulkUsb_PacketTransmit(
IN PAX_ADAPTER Adapter
);
VOID
BulkUsb_PacketReceive(
IN PAX_ADAPTER Adapter
);
VOID
BulkUsb_InterruptEvent(
IN PAX_ADAPTER Adapter
);
NTSTATUS
BulkUsb_Interrupt_Complete(
IN PDEVICE_OBJECT DeviceObject,
IN PIRP Irp,
IN PBULKUSB_RW_CONTEXT context
);
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