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📄 main.lss

📁 Mega16 + MCP3208 12bit A/D >> C-source code >> AVRSTUDIO project >> WinAVR
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     750:	0e 94 f3 01 	call	0x3e6	; 0x3e6 <usart_puts>
     754:	2f 96       	adiw	r28, 0x0f	; 15
     756:	0f b6       	in	r0, 0x3f	; 63
     758:	f8 94       	cli
     75a:	de bf       	out	0x3e, r29	; 62
     75c:	0f be       	out	0x3f, r0	; 63
     75e:	cd bf       	out	0x3d, r28	; 61
     760:	df 91       	pop	r29
     762:	cf 91       	pop	r28
     764:	1f 91       	pop	r17
     766:	0f 91       	pop	r16
     768:	08 95       	ret

0000076a <usart_SendFloat>:
     76a:	0f 93       	push	r16
     76c:	1f 93       	push	r17
     76e:	cf 93       	push	r28
     770:	df 93       	push	r29
     772:	cd b7       	in	r28, 0x3d	; 61
     774:	de b7       	in	r29, 0x3e	; 62
     776:	2f 97       	sbiw	r28, 0x0f	; 15
     778:	0f b6       	in	r0, 0x3f	; 63
     77a:	f8 94       	cli
     77c:	de bf       	out	0x3e, r29	; 62
     77e:	0f be       	out	0x3f, r0	; 63
     780:	cd bf       	out	0x3d, r28	; 61
     782:	8e 01       	movw	r16, r28
     784:	0f 5f       	subi	r16, 0xFF	; 255
     786:	1f 4f       	sbci	r17, 0xFF	; 255
     788:	0e 94 ee 04 	call	0x9dc	; 0x9dc <dtostrf>
     78c:	00 e0       	ldi	r16, 0x00	; 0
     78e:	10 e0       	ldi	r17, 0x00	; 0
     790:	02 c0       	rjmp	.+4      	; 0x796 <usart_SendFloat+0x2c>
     792:	0e 94 15 02 	call	0x42a	; 0x42a <usart_putc>
     796:	fe 01       	movw	r30, r28
     798:	31 96       	adiw	r30, 0x01	; 1
     79a:	e0 0f       	add	r30, r16
     79c:	f1 1d       	adc	r31, r1
     79e:	80 81       	ld	r24, Z
     7a0:	0f 5f       	subi	r16, 0xFF	; 255
     7a2:	1f 4f       	sbci	r17, 0xFF	; 255
     7a4:	88 23       	and	r24, r24
     7a6:	a9 f7       	brne	.-22     	; 0x792 <usart_SendFloat+0x28>
     7a8:	2f 96       	adiw	r28, 0x0f	; 15
     7aa:	0f b6       	in	r0, 0x3f	; 63
     7ac:	f8 94       	cli
     7ae:	de bf       	out	0x3e, r29	; 62
     7b0:	0f be       	out	0x3f, r0	; 63
     7b2:	cd bf       	out	0x3d, r28	; 61
     7b4:	df 91       	pop	r29
     7b6:	cf 91       	pop	r28
     7b8:	1f 91       	pop	r17
     7ba:	0f 91       	pop	r16
     7bc:	08 95       	ret

000007be <delayloop>:
#include <util/delay.h>
#include "delay.h"

void delayloop(unsigned long t) 
{
     7be:	08 95       	ret

000007c0 <delay_us>:
	unsigned int i;
	if (t==0) return;
	while (t--) for(i=0;i<K_DELAY; i++);
}

void delay_ms(unsigned long  ms) 
{ 
    unsigned long i; 
    ms *= 1000; 
    for (i=0; i < ms; i++) 
    { 
        _delay_us(1); 
    } 
} 

void delay_us(unsigned int  us) 
{ 
     7c0:	ac 01       	movw	r20, r24
     7c2:	20 e0       	ldi	r18, 0x00	; 0
     7c4:	30 e0       	ldi	r19, 0x00	; 0
     7c6:	95 e0       	ldi	r25, 0x05	; 5
     7c8:	05 c0       	rjmp	.+10     	; 0x7d4 <delay_us+0x14>
*/
void
_delay_loop_1(uint8_t __count)
{
	__asm__ volatile (
     7ca:	89 2f       	mov	r24, r25
     7cc:	8a 95       	dec	r24
     7ce:	f1 f7       	brne	.-4      	; 0x7cc <delay_us+0xc>
     7d0:	2f 5f       	subi	r18, 0xFF	; 255
     7d2:	3f 4f       	sbci	r19, 0xFF	; 255
    unsigned long i; 
	
    for (i=0; i < us; i++) 
     7d4:	24 17       	cp	r18, r20
     7d6:	35 07       	cpc	r19, r21
     7d8:	c1 f7       	brne	.-16     	; 0x7ca <delay_us+0xa>
     7da:	08 95       	ret

000007dc <delay_ms>:
     7dc:	ef 92       	push	r14
     7de:	ff 92       	push	r15
     7e0:	0f 93       	push	r16
     7e2:	1f 93       	push	r17
     7e4:	28 ee       	ldi	r18, 0xE8	; 232
     7e6:	33 e0       	ldi	r19, 0x03	; 3
     7e8:	40 e0       	ldi	r20, 0x00	; 0
     7ea:	50 e0       	ldi	r21, 0x00	; 0
     7ec:	0e 94 99 04 	call	0x932	; 0x932 <__mulsi3>
     7f0:	7b 01       	movw	r14, r22
     7f2:	8c 01       	movw	r16, r24
     7f4:	20 e0       	ldi	r18, 0x00	; 0
     7f6:	30 e0       	ldi	r19, 0x00	; 0
     7f8:	40 e0       	ldi	r20, 0x00	; 0
     7fa:	50 e0       	ldi	r21, 0x00	; 0
     7fc:	95 e0       	ldi	r25, 0x05	; 5
     7fe:	07 c0       	rjmp	.+14     	; 0x80e <delay_ms+0x32>
*/
void
_delay_loop_1(uint8_t __count)
{
	__asm__ volatile (
     800:	89 2f       	mov	r24, r25
     802:	8a 95       	dec	r24
     804:	f1 f7       	brne	.-4      	; 0x802 <delay_ms+0x26>
     806:	2f 5f       	subi	r18, 0xFF	; 255
     808:	3f 4f       	sbci	r19, 0xFF	; 255
     80a:	4f 4f       	sbci	r20, 0xFF	; 255
     80c:	5f 4f       	sbci	r21, 0xFF	; 255
     80e:	2e 15       	cp	r18, r14
     810:	3f 05       	cpc	r19, r15
     812:	40 07       	cpc	r20, r16
     814:	51 07       	cpc	r21, r17
     816:	a1 f7       	brne	.-24     	; 0x800 <delay_ms+0x24>
     818:	1f 91       	pop	r17
     81a:	0f 91       	pop	r16
     81c:	ff 90       	pop	r15
     81e:	ef 90       	pop	r14
     820:	08 95       	ret

00000822 <MCP3208_spiDelay>:
#include "mcp3208.h"


void MCP3208_spiDelay(unsigned int NOPcount)
{
     822:	20 e0       	ldi	r18, 0x00	; 0
     824:	30 e0       	ldi	r19, 0x00	; 0
	unsigned int n;
	for(n=0;n<=NOPcount;n++)
	{
		asm volatile ("nop" ::);
     826:	00 00       	nop
     828:	2f 5f       	subi	r18, 0xFF	; 255
     82a:	3f 4f       	sbci	r19, 0xFF	; 255
     82c:	82 17       	cp	r24, r18
     82e:	93 07       	cpc	r25, r19
     830:	d0 f7       	brcc	.-12     	; 0x826 <MCP3208_spiDelay+0x4>
     832:	08 95       	ret

00000834 <MCP3208_spiInit>:
	}
}

void MCP3208_spiInit(void)
{
     834:	80 eb       	ldi	r24, 0xB0	; 176
     836:	87 bb       	out	0x17, r24	; 23
    // Set MOSI, SCK and ENB output, all other input
    DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS);  // set DD_SS to output

    // Enable SPI, Master, set clock rate fclk/64 
	// Setup (Falling) Sample (Rising) SPI set mode 3 
	// CPOL=1 : CPHA=1
	SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR1)|(0<<SPR0)|(1<<CPOL)|(1<<CPHA);
     838:	8e e5       	ldi	r24, 0x5E	; 94
     83a:	8d b9       	out	0x0d, r24	; 13
	PORT_SPI |= (1<<(PIN_CS));    //setbitHigh CS   Pin
     83c:	c4 9a       	sbi	0x18, 4	; 24
	PORT_SPI |= (1<<(PIN_MOSI));  //setbitHigh MOSI Pin
     83e:	c5 9a       	sbi	0x18, 5	; 24
	PORT_SPI |= (1<<(PIN_CLK));   //setbitHigh CLK  Pin
     840:	c7 9a       	sbi	0x18, 7	; 24
     842:	08 95       	ret

00000844 <MCP3208_spiWrite>:
}

unsigned char MCP3208_spiWrite(char cData)
{        
     844:	8f b9       	out	0x0f, r24	; 15
    // Start transmission
    SPDR = cData;                   
    // Wait for transmission complete
    while (!(SPSR & (1<<SPIF)))   
     846:	77 9b       	sbis	0x0e, 7	; 14
     848:	fe cf       	rjmp	.-4      	; 0x846 <MCP3208_spiWrite+0x2>
        ;
    return SPDR;
     84a:	8f b1       	in	r24, 0x0f	; 15
}
     84c:	99 27       	eor	r25, r25
     84e:	08 95       	ret

00000850 <MCP3208_spiRead>:

unsigned int MCP3208_spiRead(unsigned char AD_type,unsigned char ADchanel)
{
     850:	28 2f       	mov	r18, r24
	unsigned char  tempHigh,tempLow,tempADtype,dumyData;

    PORT_SPI &= ~(1<<(PIN_CS));     //setbitLow CS  Pin
     852:	c4 98       	cbi	0x18, 4	; 24
     854:	80 e0       	ldi	r24, 0x00	; 0
     856:	90 e0       	ldi	r25, 0x00	; 0
     858:	00 00       	nop
     85a:	01 96       	adiw	r24, 0x01	; 1
     85c:	81 31       	cpi	r24, 0x11	; 17
     85e:	91 05       	cpc	r25, r1
     860:	d9 f7       	brne	.-10     	; 0x858 <MCP3208_spiRead+0x8>
	MCP3208_spiDelay(delayCount );

	tempADtype = (AD_type & 0x01) << 1 ;
	tempLow = (ADchanel & 0x03) << 6;	
    tempHigh = (ADchanel & 0x04) >> 2;	
     862:	86 2f       	mov	r24, r22
     864:	99 27       	eor	r25, r25
     866:	84 70       	andi	r24, 0x04	; 4
     868:	90 70       	andi	r25, 0x00	; 0
     86a:	95 95       	asr	r25
     86c:	87 95       	ror	r24
     86e:	95 95       	asr	r25
     870:	87 95       	ror	r24
     872:	21 70       	andi	r18, 0x01	; 1
     874:	22 0f       	add	r18, r18
     876:	24 60       	ori	r18, 0x04	; 4
     878:	28 2b       	or	r18, r24
     87a:	2f b9       	out	0x0f, r18	; 15
     87c:	77 9b       	sbis	0x0e, 7	; 14
     87e:	fe cf       	rjmp	.-4      	; 0x87c <MCP3208_spiRead+0x2c>
     880:	8f b1       	in	r24, 0x0f	; 15
     882:	62 95       	swap	r22
     884:	66 0f       	add	r22, r22
     886:	66 0f       	add	r22, r22
     888:	60 7c       	andi	r22, 0xC0	; 192
     88a:	6f b9       	out	0x0f, r22	; 15
     88c:	77 9b       	sbis	0x0e, 7	; 14
     88e:	fe cf       	rjmp	.-4      	; 0x88c <MCP3208_spiRead+0x3c>
     890:	8f b1       	in	r24, 0x0f	; 15
	tempHigh |= (0x04)|(tempADtype);     // 0x04 --> startBit

	dumyData = MCP3208_spiWrite(tempHigh);  	  // Write control HighByte return not care
    gReciveHighByte = MCP3208_spiWrite(tempLow);  // Write control LowByte return A/D-MSB data
     892:	99 27       	eor	r25, r25
     894:	80 93 7b 01 	sts	0x017B, r24
     898:	1f b8       	out	0x0f, r1	; 15
     89a:	77 9b       	sbis	0x0e, 7	; 14
     89c:	fe cf       	rjmp	.-4      	; 0x89a <MCP3208_spiRead+0x4a>
     89e:	8f b1       	in	r24, 0x0f	; 15
    gReciveLowByte = MCP3208_spiWrite(0x00);      // Write Null byte 0x00 return A/D-LSB data
     8a0:	99 27       	eor	r25, r25
     8a2:	80 93 7c 01 	sts	0x017C, r24
     8a6:	80 e0       	ldi	r24, 0x00	; 0
     8a8:	90 e0       	ldi	r25, 0x00	; 0
     8aa:	00 00       	nop
     8ac:	01 96       	adiw	r24, 0x01	; 1
     8ae:	81 31       	cpi	r24, 0x11	; 17
     8b0:	91 05       	cpc	r25, r1
     8b2:	d9 f7       	brne	.-10     	; 0x8aa <MCP3208_spiRead+0x5a>

	MCP3208_spiDelay(delayCount );
    PORT_SPI |= (1<<(PIN_CS));	    //setbitHigh CS  Pin
     8b4:	c4 9a       	sbi	0x18, 4	; 24

	return (((gReciveHighByte & 0x0F)<<8)|gReciveLowByte);  // return 16bit variable (12bit A/D data)
     8b6:	80 91 7b 01 	lds	r24, 0x017B
     8ba:	20 91 7c 01 	lds	r18, 0x017C
     8be:	99 27       	eor	r25, r25
     8c0:	8f 70       	andi	r24, 0x0F	; 15
     8c2:	90 70       	andi	r25, 0x00	; 0
     8c4:	98 2f       	mov	r25, r24
     8c6:	88 27       	eor	r24, r24
     8c8:	33 27       	eor	r19, r19
}
     8ca:	82 2b       	or	r24, r18
     8cc:	93 2b       	or	r25, r19
     8ce:	08 95       	ret

000008d0 <itoa>:
     8d0:	fb 01       	movw	r30, r22
     8d2:	9f 01       	movw	r18, r30
     8d4:	e8 94       	clt
     8d6:	42 30       	cpi	r20, 0x02	; 2
     8d8:	c4 f0       	brlt	.+48     	; 0x90a <itoa+0x3a>
     8da:	45 32       	cpi	r20, 0x25	; 37
     8dc:	b4 f4       	brge	.+44     	; 0x90a <itoa+0x3a>
     8de:	4a 30       	cpi	r20, 0x0A	; 10
     8e0:	29 f4       	brne	.+10     	; 0x8ec <itoa+0x1c>
     8e2:	97 fb       	bst	r25, 7
     8e4:	1e f4       	brtc	.+6      	; 0x8ec <itoa+0x1c>
     8e6:	90 95       	com	r25
     8e8:	81 95       	neg	r24
     8ea:	9f 4f       	sbci	r25, 0xFF	; 255
     8ec:	64 2f       	mov	r22, r20
     8ee:	77 27       	eor	r23, r23
     8f0:	0e 94 b8 04 	call	0x970	; 0x970 <__udivmodhi4>
     8f4:	80 5d       	subi	r24, 0xD0	; 208
     8f6:	8a 33       	cpi	r24, 0x3A	; 58
     8f8:	0c f0       	brlt	.+2      	; 0x8fc <itoa+0x2c>
     8fa:	89 5d       	subi	r24, 0xD9	; 217
     8fc:	81 93       	st	Z+, r24
     8fe:	cb 01       	movw	r24, r22
     900:	00 97       	sbiw	r24, 0x00	; 0
     902:	a1 f7       	brne	.-24     	; 0x8ec <itoa+0x1c>
     904:	16 f4       	brtc	.+4      	; 0x90a <itoa+0x3a>
     906:	5d e2       	ldi	r21, 0x2D	; 45
     908:	51 93       	st	Z+, r21
     90a:	10 82       	st	Z, r1
     90c:	c9 01       	movw	r24, r18
     90e:	0c 94 89 04 	jmp	0x912	; 0x912 <strrev>

00000912 <strrev>:
     912:	dc 01       	movw	r26, r24
     914:	fc 01       	movw	r30, r24
     916:	67 2f       	mov	r22, r23
     918:	71 91       	ld	r23, Z+
     91a:	77 23       	and	r23, r23
     91c:	e1 f7       	brne	.-8      	; 0x916 <strrev+0x4>
     91e:	32 97       	sbiw	r30, 0x02	; 2
     920:	04 c0       	rjmp	.+8      	; 0x92a <strrev+0x18>
     922:	7c 91       	ld	r23, X
     924:	6d 93       	st	X+, r22
     926:	70 83       	st	Z, r23
     928:	62 91       	ld	r22, -Z
     92a:	ae 17       	cp	r26, r30
     92c:	bf 07       	cpc	r27, r31
     92e:	c8 f3       	brcs	.-14     	; 0x922 <strrev+0x10>
     930:	08 95       	ret

00000932 <__mulsi3>:
     932:	62 9f       	mul	r22, r18
     934:	d0 01       	movw	r26, r0
     936:	73 9f       	mul	r23, r19
     938:	f0 01       	movw	r30, r0
     93a:	82 9f       	mul	r24, r18
     93c:	e0 0d       	add	r30, r0
     93e:	f1 1d       	adc	r31, r1
     940:	64 9f       	mul	r22, r20
     942:	e0 0d       	add	r30, r0
     944:	f1 1d       	adc	r31, r1
     946:	92 9f       	mul	r25, r18
     948:	f0 0d       	add	r31, r0
     94a:	83 9f       	mul	r24, r19
     94c:	f0 0d       	add	r31, r0
     94e:	74 9f       	mul	r23, r20
     950:	f0 0d       	add	r31, r0
     952:	65 9f       	mul	r22, r21

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