📄 etherdev.h
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#ifndef ETHERDEV_H
#define ETHERDEV_H
#include "reg51.h"
#include <absacc.h>
/****以下配置需要按照单板具体情况修改************/
/*寄存器读写地址*/
#define reg00 XBYTE[0x8000] /* 300H */
#define reg01 XBYTE[0x8001] /* 301H*/
#define reg02 XBYTE[0x8002]
#define reg03 XBYTE[0x8003]
#define reg04 XBYTE[0x8004]
#define reg05 XBYTE[0x8005]
#define reg06 XBYTE[0x8006]
#define reg07 XBYTE[0x8007]
#define reg08 XBYTE[0x8008]
#define reg09 XBYTE[0x8009]
#define reg0a XBYTE[0x800a]
#define reg0b XBYTE[0x800b]
#define reg0c XBYTE[0x800c]
#define reg0d XBYTE[0x800d]
#define reg0e XBYTE[0x800e]
#define reg0f XBYTE[0x800f]
#define reg10 XBYTE[0x8010]
#define reg18 XBYTE[0x8018]
#define reg1c XBYTE[0x801c] /* 31cH*/
#define reg1f XBYTE[0x801f] /* 31fH*/
/*单片机外部晶振*/
#define ETH_CPU_XTAL 20000000
/****以上配置需要按照单板具体情况修改************/
#define CR reg00 // Control register
// Control register bits
#define PS1 0x80 // Page select bit 1 1000 000
#define PS0 0x40 // Page select bit 0
#define RD2 0x20 // Remote DMA control bit 2
#define RD1 0x10 // Remote DMA control bit 1
#define RD0 0x08 // Remote DMA control bit 0
#define TXP 0x04 // Transmit packet bit
#define STA 0x02 // Start bit (a flag only)
#define STP 0x01 // Stop bit transceiver ctrl
#define RDMA_REG reg10 // Remote DMA port
#define RESET_REG reg18 // Reset port 0001 1000
// Page 0 read/write registers.
#define BNRY reg03 // Boundary register
#define ISR reg07 // Interrupt status register
// Interrupt status register bits
#define RST 0x80 // Reset state indicator bit
#define RDC 0x40 // Remote DMA complete bit
#define CNT 0x20 // Network tally counter MSB set
#define OVW 0x10 // Receive buffer exhausted
#define TXE 0x08 // Transmit abort error bit
#define RXE 0x04 // Receive error report bit
#define PTX 0x02 // Successful packet transmit
#define PRX 0x01 // Successful packet receive
// Page 0 read only registers.
#define CLDA0 reg01
#define CLDA1 reg02
#define TSR reg04
#define NCR reg05
#define FIFO reg06
#define CRDA0 reg08
#define CRDA1 reg09
#define _8019ID0 reg0a
#define _8019ID1 reg0b
#define RSR reg0c
#define CNTR0 reg0d
#define CNTR1 reg0e
#define CNTR2 reg0f
// Page 0 write only registers.
#define PSTART reg01 // Receive page start register
#define PSTOP reg02 // Receive page stop register
#define TPSR reg04 // Transmit page start register
#define TBCR0 reg05 // Transmit byte count register 0
#define TBCR1 reg06 // Transmit byte count register 1
#define RSAR0 reg08 // Remote start address register 0
#define RSAR1 reg09 // Remote start address register 0
#define RBCR0 reg0a // Remote byte count register 0
#define RBCR1 reg0b // Remote byte count register 1
#define RCR reg0c // Receive configuration register
// Receive configuration register bits (write in page 0, read in page 2)
#define MON 0x20 // Monitor mode select bit
#define PRO 0x10 // Promiscuous mode select bit
#define AM 0x08 // Multicast packet accept bit
#define AB 0x04 // Broadcast packet accept bit
#define AR 0x02 // Runt packet accept bit
#define SEP 0x01 // Error packet accept bit
#define TCR reg0d // Transmit configuration register
// Transmit configuration register bits
#define OFST 0x10 // Collision offset enable bit
#define ATD 0x08 // Auto transmit disable select bit
#define LB1 0x04 // Loopback mode select bit 1
#define LB0 0x02 // Loopback mode select bit 0
#define CRC 0x01 // CRC generation inhibit bit
#define DCR reg0e // Data configuration register
// Data configuration register bits (write in page 0, read in page 2)
#define FT1 0x40 // FIFO threshold select bit 1
#define FT0 0x20 // FIFO threshold select bit 0
#define ARM 0x10 // Auto-initialise remote
#define LS 0x08 // Loopback select bit
#define LAS 0x04 // Set to 0 (pwrup = 1)
#define BOS 0x02 // Byte order select bit
#define WTS 0x01 // Word transfer select bit
#define IMR reg0f // Interrupt mask register
// Interrupt mask register bits
// Each enable bit correspons with an interrupt flag in ISR
// Page 1 read/write registers.
#define PAR0 reg01 // Physical address register 0
#define PAR1 reg02 // Physical address register 1
#define PAR2 reg03 // Physical address register 2
#define PAR3 reg04 // Physical address register 3
#define PAR4 reg05 // Physical address register 4
#define PAR5 reg06 // Physical address register 5
#define CURR reg07 // Current receive buffer page
#define MAR0 reg08
#define MAR1 reg09
#define MAR2 reg0a
#define MAR3 reg0b
#define MAR4 reg0c
#define MAR5 reg0d
#define MAR6 reg0e
#define MAR7 reg0f
// Page 3 read/write registers.
#define _9346CR reg01 // 9346 EEPROM command register
// 9346 EEPROM command register bits
#define EEM1 0x80 // RTL8019AS operating mode bit 1
#define EEM0 0x40 // RTL8019AS operating mode bit 0
#define EECS 0x08 // 9346 EEPROM chip select bit
#define EESK 0x04 // 9346 EEPROM serial clock bit
#define EEDI 0x02 // 9346 EEPROM data input bit
#define EEDO 0x01 // 9346 EEPROM data output bit
#define BPAGE reg02
#define CONFIG1 reg04 // RTL9019AS config register 1
// RTL9019AS config register 1 bits
#define IRQEN 0x80 // IRQ enable bit (WR protected)
#define IRQS2 0x40 // IRQ line select bit 2
#define IRQS1 0x20 // IRQ line select bit 1
#define IRQS0 0x10 // IRQ line select bit 0
#define IOS3 0x08 // I/O base address select bit 3
#define IOS2 0x04 // I/O base address select bit 2
#define IOS1 0x02 // I/O base address select bit 1
#define IOS0 0x01 // I/O base address select bit 0
#define CONFIG2 reg05 //
// RTL9019AS config register 2 bits
#define PL1 0x80 // Network medium type select bit 1
#define PL0 0x40 // Network medium type select bit 0
#define BSELB 0x20 // Boot ROM disable (WR protected)
#define BS4 0x10 // Boot ROM configuration bit 4
#define BS3 0x08 // Boot ROM configuration bit 3
#define BS2 0x04 // Boot ROM configuration bit 2
#define BS1 0x02 // Boot ROM configuration bit 1
#define BS0 0x01 // Boot ROM configuration bit 0
#define CONFIG3 reg06 // RTL9019AS config register 3
// RTL9019AS config register 3 bits
#define PNP 0x80 // Plug & play mode indicator bit
#define FUDUP 0x40 // Full duplex mode select bit
#define LEDS1 0x20 // LED output select bit 1
#define LEDS0 0x10 // LED output select bit 0
#define SLEEP 0x04 // Sleep mode select bit
#define PWRDN 0x02 // Power down mode select bit
#define ACTIVEB 0x01 // Inverse of bit 0, PNP active reg
// Page 3 read only registers.
#define CONFIG0 reg03 // RTL9019AS config register 0
// RTL9019AS config register 0 bits
#define VERID1 0x80 // RTL9019AS version ID bit 1 (R/W)
#define VERID0 0x40 // RTL9019AS version ID bit 0 (R/W)
#define AUI 0x20 // AUI input pin state bit
#define PNPJP 0x10 // PNP jumper pin state bit
#define JP 0x08 // JP input pin state bit
#define BNC 0x04 // Thinnet mode indication bit
#define CSNSAV reg08
#define INTR reg0b
#define CONFIG4 reg0d
// Page 3 write only registers.
#define TEST reg07
#define HLTCLK reg09
#define FMWP reg0c
#define ETH_CPU_CLOCK ETH_CPU_XTAL / 12 // 8051 clock rate (X1 mode)
#define ETH_DELAY_CONST 9.114584e-5 // Delay routine constant
#define ETH_DELAY_MULTPLR (unsigned char)(ETH_DELAY_CONST * ETH_CPU_CLOCK)
#define ETH_TX_PAGE_START 0x40 // 0x4000 Tx buffer is 6 * 256 = 1536 bytes
#define ETH_RX_PAGE_START 0x46 // 0x4600 Rx buffer
#define ETH_RX_PAGE_STOP 0x80 // 0x6000
#define ETH_ADDR_PORT_MASK 0x1F // 00011111y
#define ETH_DATA_PORT_MASK 0xFF // 11111111y
#define ETH_MIN_PACKET_LEN 0x3C
void etherdev_init(void);
void etherdev_send(void);
unsigned int etherdev_read(void);
#endif
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