play_capture.c

Sample code for use on smp 863x processor.

	} else {
		//fprintf(stderr, "\n\n  -- DISABLE SiI9031 Audio --\n\n\n");
		err = write_i2c(pInstance, delay, dev + 4, 0x27, 0x01);  // Disable I2S0 out and MClk, send PCM only on I2S
		err = write_i2c(pInstance, delay, dev + 4, 0x29, 0x30);  // Disable I2S and SPDIF signals
	}
	err = write_i2c(pInstance, delay, dev, 0x05, 0xD2); // reset of audio FIFO, put HDCP and ACR in auto-reset
	err = write_i2c(pInstance, delay, dev, 0x05, 0xD0); // end reset
	
	return RM_OK;
}

static RMstatus tristate_AD9883(
	struct RUA *pInstance, 
	RMuint8 delay, 
	RMuint8 dev)
{
	RMstatus err;
	err = write_i2c(pInstance, delay, dev, 0x0F, 0x4C); // power down AD9883A
	return err;
}

static RMstatus tristate_SiI9031(
	struct RUA *pInstance, 
	RMuint8 delay, 
	RMuint8 dev)
{
	RMstatus err;
	err = write_i2c(pInstance, delay, dev, 0x08, 0x06); // power down SiI9031
	err = write_i2c(pInstance, delay, dev, 0x09, 0x00); // tri-state SiI9031
	err = write_i2c(pInstance, delay, dev + 4, 0x27, 0x01); // Disable I2S out and MClk
	err = write_i2c(pInstance, delay, dev + 4, 0x29, 0x18); // Disable I2S signals
	err = write_i2c(pInstance, delay, dev + 4, 0x3C, 0x00); // power down and tri-state chip.
	err = write_i2c(pInstance, delay, dev + 4, 0x3E, 0x00); // power down and tri-state chip.
	err = write_i2c(pInstance, delay, dev + 4, 0x3F, 0x00); // power down and tri-state chip.
	return err;
}

static RMstatus tristate_SAA7119(
	struct RUA *pInstance, 
	RMuint8 delay, 
	RMuint8 dev)
{
	RMstatus err;
	err = write_i2c(pInstance, delay, dev, 0x83, 0x10); // tri-state xport
	err = write_i2c(pInstance, delay, dev, 0x87, 0x10); // tri-state iport
	err = write_i2c(pInstance, delay, dev, 0x88, 0x0D); // reset and power down scaler, tri-state audio clocks
	return err;
}

static RMstatus init_capture_AD9883(
	struct RUA *pInstance, 
	struct capture_cmdline *capture_opt, 
	struct local_cmdline *local_opt, 
	struct audio_cmdline *audio_opt, 
	RMuint8 dev, 
	RMuint8 delay)
{
	RMstatus err;
	RMuint8 range, current;
	struct EMhwlibTVFormatDigital fmt;
	RMuint32 vcogain, postdiv, plldiv, bp;
	RMreal c;
	RMbool yuv;
	
	// Analog Devices 9883 setup
	RMuint8 i2c_data[][2] = {
		{0x01, 0x69},  // PLL Div MSB
		{0x02, 0xD0},  // PLL Div LSB
		{0x03, 0x48},  // VCO
		{0x04, 0x80},  // Phase adj.
		{0x05, 0x80},  // Clamp plcemnt.
		{0x06, 0x80},  // Clamp dur.
		{0x07, 0x20},  // HSync out width
		{0x08, 0x80},  // R gain
		{0x09, 0x80},  // G gain
		{0x0a, 0x80},  // B gain
		{0x0b, 0x80},  // R offs.
		{0x0c, 0x80},  // G offs.
		{0x0d, 0x80},  // B offs.
		{0x0e, 0x40},  // Sync ctrl.
		{0x0f, 0x6E},  // Ctrl.
		{0x10, 0xB8},  // SOG Thr.
		{0x11, 0x20},  // Sync Sep. Thr.
		{0x12, 0x01},  // Pre-Coast
		{0x13, 0x01},  // Post-Coast
		{0x15, 0xFE},  // Test reg.
	};
	
	err = RUAExchangeProperty(pInstance, DisplayBlock, 
		RMDisplayBlockPropertyID_TVFormatDigital, 
		&(capture_opt->TVStandard), sizeof(capture_opt->TVStandard), 
		&fmt, sizeof(fmt));
	if (RMFAILED(err)) fprintf(stderr, "Failed to get TV format, %s\n", RMstatusToString(err));
	
	vcogain = 150;
	postdiv = 1;
	if (fmt.PixelClock < 32000000) {
		range = 0;
		postdiv = 4;
	} else if (fmt.PixelClock < 64000000) {
		range = 1;
		postdiv = 2;
	} else if (fmt.PixelClock < 125000000) {
		range = 2;
	} else {
		range = 3;
		vcogain = 180;
	}
	plldiv = fmt.HTotalSize;
	
	// Formula from AD's Excel sheet 249461068RevAD9883_PLL.xls:
	// c=((HFreq*6.28/((PixClk<32000000)?12.5:15))^2*((0.082*0.000001*plldiv*postdiv)/(vcogain*1000000))*1000000
	c = fmt.PixelClock;
	c *= 6.28 / fmt.HTotalSize;
	c /= ((fmt.PixelClock < 32000000) ? 12.5 : 15.0);
	c *= c;
	c *= (0.082 * plldiv * postdiv) / (vcogain * 1000000.0);
	current = 
		(c <   75.0) ? 0 : 
		(c <  125.0) ? 1 : 
		(c <  200.0) ? 2 : 
		(c <  300.0) ? 3 : 
		(c <  425.0) ? 4 : 
		(c <  625.0) ? 5 : 
		(c < 1125.0) ? 6 : 
		               7;
	fprintf(stderr, "AD9883 calc - PixClk=%lu range=%u c=%f current=%u\n", fmt.PixelClock, range, c, current);
	
	bp = fmt.XOffset - fmt.HSyncWidth;  // BackPorch
	yuv = (local_opt->i2c_port == cap_Component1);  // sync on green
	
	i2c_data[0x01 - 1][1] = (plldiv >> 4) & 0xFF;
	i2c_data[0x02 - 1][1] = (plldiv << 4) & 0xF0;
	i2c_data[0x03 - 1][1] = (range << 6) | (current << 3);
	i2c_data[0x05 - 1][1] = (bp >= 4) ? 0x04 : (bp / 4);  // clamp placement
	i2c_data[0x06 - 1][1] = (bp >= 4) ? (bp - 8) : (bp / 2);  // clamp duration
	
	//i2c_data[0x07 - 1][1] = fmt.HSyncWidth;  // TODO
	i2c_data[0x07 - 1][1] = 0x10;
	
	// set contrast
	i2c_data[0x08 - 1][1] = yuv ? 0x80 : 0xF0;  // R gain
	i2c_data[0x09 - 1][1] = yuv ? 0x80 : 0xF0;  // G gain
	i2c_data[0x0A - 1][1] = yuv ? 0x80 : 0xF0;  // B gain
	
	// set brightness
	i2c_data[0x0B - 1][1] = yuv ? 0x60 : 0x80;  // R offs
	i2c_data[0x0C - 1][1] = yuv ? 0x80 : 0x80;  // G offs
	i2c_data[0x0D - 1][1] = yuv ? 0x60 : 0x80;  // B offs
	
	i2c_data[0x0E - 1][1] |= yuv ? 0x1B : 0x10;  // select sync source, sog or h-sync. force vsync from sog for yuv.
	i2c_data[0x10 - 1][1] |= yuv ? 0x05 : 0x00;  // clamp red and blue to center for YUV
	
	err = init_i2c(pInstance, delay, dev, i2c_data, sizeof(i2c_data) / sizeof (RMuint8) / 2);
	
	return err;
}

static RMstatus set_cable_comp_SiI9031(
	struct RUA *pInstance, 
	struct capture_cmdline *capture_opt, 
	struct local_cmdline *local_opt, 
	RMuint8 dev, 
	RMuint8 delay)
{
	RMuint8 eq;
	
	eq = local_opt->cable_eq & 0x0F;
	eq = (eq << 4) | (0x0F - eq);
	return write_i2c(pInstance, delay, dev, 0x81, eq);
}

static RMstatus set_422_to_444_upsampling_SiI9031(
	struct RUA *pInstance, 
	RMbool upsampling, 
	RMuint8 dev, 
	RMuint8 delay)
{
	RMstatus err;
	RMuint32 reg;
	
	err = read_i2c(pInstance, delay, dev, 0x4A, &reg);
	if (RMFAILED(err)) reg = 0x01;  // default value
	if (upsampling) reg |= 0x04;
	else reg &= ~0x04;
	err = write_i2c(pInstance, delay, dev, 0x4A, reg);
	
	return err;
}

static RMstatus set_blanking_color_SiI9031(
	struct RUA *pInstance, 
	struct capture_cmdline *capture_opt, 
	struct local_cmdline *local_opt, 
	RMuint8 dev, 
	RMuint8 delay)
{
	RMstatus err;
	RMuint8 r, g, b;
	
	r = g = b = 0x00;
	
	if (
		(capture_opt->InputColorSpace != EMhwlibColorSpace_RGB_0_255) && 
		(capture_opt->InputColorSpace != EMhwlibColorSpace_RGB_16_235)
	) {
		//rgb_to_yuv(r, g, b, &g, &b, &r);
		g = 0x10;
		r = b = 0x80;
	}
	
	err = write_i2c(pInstance, delay, dev, 0x4B, b);
	if (RMFAILED(err)) RMDBGLOG((ENABLE, "Error writing I2C!\n"));
	err = write_i2c(pInstance, delay, dev, 0x4C, g);
	if (RMFAILED(err)) RMDBGLOG((ENABLE, "Error writing I2C!\n"));
	err = write_i2c(pInstance, delay, dev, 0x4D, r);
	if (RMFAILED(err)) RMDBGLOG((ENABLE, "Error writing I2C!\n"));
	
	return RM_OK;
}

static RMstatus apply_pixelrep_SiI9031(
	struct RUA *pRUA, 
	RMuint8 dev, 
	RMuint8 delay, 
	RMuint32 pixel_rep)
{
	RMstatus err;
	RMuint32 reg;
	
	err = read_i2c(pRUA, delay, dev, 0x08, &reg);
	if (RMFAILED(err)) return err;
	if ((pixel_rep == 1) || (pixel_rep == 3)) {
		RMinsShiftBits(&reg, pixel_rep, 2, 6);  // pixel clock reduction by factor 2 or 4
	} else {
		RMinsShiftBits(&reg, 0, 2, 6);  // no pixel clock reduction
	}
	err = write_i2c(pRUA, delay, dev, 0x08, reg);
	if (RMFAILED(err)) return err;
	
	return ((pixel_rep == 0) || (pixel_rep == 1) || (pixel_rep == 3)) ? RM_OK : RM_NOT_SUPPORTED;
}

static RMstatus init_capture_SiI9031(
	struct RUA *pInstance, 
	struct capture_cmdline *capture_opt, 
	struct local_cmdline *local_opt, 
	struct audio_cmdline *audio_opt, 
	RMuint8 dev, 
	RMuint8 delay)
{
	RMstatus err;
	
	// Silicon Image 9031 setup
	RMuint8 i2c_data[][2] = {
		{0x05, 0xD0},  // end reset, enable auto reset modes
		{0x08, 0x07},  // start chip, invert clock (setup on pos edge)
		{0x09, 0x11},  // select input 0
		{0x4A, 0x01},  // CCIR601, RGB 4:4:4 24 bit
		{0x49, 0x01},  // RGB input
		{0x48, 0x00},  // BT601 output colorspace
		{0x7A, 0x3F},  // ip_ctrl: initially, intr on all frames
		{0x88, 0x88},  // ACR1 magic value
		{0x89, 0x16},  // ACR2 magic value
		{0xB5, 0x00},  // disable auto audio control incl. I2S outputs
		{0xB6, 0xF3},  // enable mute conditions
		{0xB7, 0xF0},  //   "     "       "
		{0xB8, 0x07},  //   "     "       "
		{0xBB, 0x01},  // enable clear of error counts
	};
	RMuint8 i2c_data_ext[][2] = {
		//{0xBF, 0x85},  // default: receive MPEG frames in MPEG area
		{0xBF, 0x05},  // receive ISRC1 frames in MPEG area
	};
	
	if (local_opt->intr_debug) {
		local_opt->intr_mask[0] = 0x7F;  // intr1_mask: all but acrhwcts
		local_opt->intr_mask[1] = 0xB9;  // intr2_mask: all but vsync, gotcts, gotaud
		local_opt->intr_mask[2] = 0x7F;  // intr3_mask: all but new_cp
		local_opt->intr_mask[3] = 0x7F;  // intr4_mask: all
		local_opt->intr_mask[4] = 0xFF;  // intr5_mask: all
		local_opt->intr_mask[5] = 0x05;  // intr6_mask: all
	} else {
		local_opt->intr_mask[0] = 0x1B;  // intr1_mask: acrpllul, audferr, authstart, authdone
		local_opt->intr_mask[1] = 0x99;  // intr2_mask: hdmimode, ckdt, scdt, vidchg
//		local_opt->intr_mask[2] = 0x3F;  // intr3_mask: spdif_err, newunr, newmpeg, newaud, newspd, newavi
		local_opt->intr_mask[2] = 0x2F;  // intr3_mask: spdif_err, newmpeg, newaud, newspd, newavi
//		local_opt->intr_mask[2] = 0x0F;  // intr3_mask: newmpeg, newaud, newspd, newavi
		local_opt->intr_mask[3] = 0x1F;  // intr4_mask: no_avi, cts_drop, cts_reuse, fifo_over, fifo_under
//		local_opt->intr_mask[3] = 0x1C;  // intr4_mask: no_avi, cts_drop, cts_reuse
		local_opt->intr_mask[4] = 0xFF;  // intr5_mask: fnchg, aac_mute, aul_err, vrchg, hrchg, pochg, ilchg, fschg
		local_opt->intr_mask[5] = 0x05;  // intr6_mask: new_acp, unplug
	}
	
	if (local_opt->i2c_port == cap_HDMI1) {
		i2c_data[2][1] = 0x22;  // select input 1
	}
	
	// for pioneer video card (8620L/8bit/656):
	if (local_opt->i2c_board == cap_pioneer809e1video) {
		i2c_data[3][1] = 0xFB;  // CCIR656, convert RGB 4:4:4 24 bit to YUV 4:2:2 8+8 bit
		i2c_data[5][1] = 0x01;  // BT709 output colorspace
	}
	
	if (local_opt->last_avi.valid && ((local_opt->last_avi.pixel_rep == 1) || (local_opt->last_avi.pixel_rep == 3))) {
		RMinsShiftBits(&(i2c_data[1][1]), local_opt->last_avi.pixel_rep, 2, 6);
	}
	err = write_i2c(pInstance, delay, dev + 4, 0x3C, 0x01); // power up chip.
	err = write_i2c(pInstance, delay, dev + 4, 0x3E, 0xFF); // power up chip.
	err = write_i2c(pInstance, delay, dev + 4, 0x3F, 0xFF); // power up chip.
	err = write_i2c(pInstance, delay, dev, 0x05, 0xC3); // reset of audio FIFO and chip, put HDCP and ACR in auto-reset
//	err = write_i2c(pInstance, delay, dev, 0x05, 0x0F); // reset
	err = init_i2c(pInstance, delay, dev, i2c_data, sizeof(i2c_data) / sizeof (RMuint8) / 2);
	if (RMFAILED(err)) {
		fprintf(stderr, "Failed to init SiI9031!\n");
		return err;
	}
	err = write_i2c(pInstance, delay, dev, 0x75, local_opt->intr_mask[0]);
	err = write_i2c(pInstance, delay, dev, 0x76, local_opt->intr_mask[1]);
	err = write_i2c(pInstance, delay, dev, 0x77, local_opt->intr_mask[2]);
	err = write_i2c(pInstance, delay, dev, 0x78, local_opt->intr_mask[3]);
	err = write_i2c(pInstance, delay, dev, 0x7D, local_opt->intr_mask[4]);
	err = write_i2c(pInstance, delay, dev, 0x7E, local_opt->intr_mask[5]);
	err = init_i2c(pInstance, delay, dev + 4, i2c_data_ext, sizeof(i2c_data_ext) / sizeof (RMuint8) / 2);
	if (RMFAILED(err)) {
		fprintf(stderr, "Failed to init SiI9031!\n");
		return err;
	}
	
	init_capture_SiI9031_amclk(pInstance, dev, delay, local_opt->hdmi_mode == mode_HDMI, ((audio_opt->mclk == MClkFactor_256Xfs) ? 256 : 128));
	set_cable_comp_SiI9031(pInstance, capture_opt, local_opt, dev, delay);
	set_blanking_color_SiI9031(pInstance, capture_opt, local_opt, dev, delay);
	set_422_to_444_upsampling_SiI9031(pInstance, local_opt->upsample_from_422, dev, delay);
	//HCInit();
	
	return err;
}

RMuint8 edid_info[0x80] = {
	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 
	0x40, 0xf3, 0x11, 0x03, 0xa4, 0x0c, 0x00, 0x00, 
	0x0e, 0x0e, 0x01, 0x03, 0x81, 0x22, 0x1b, 0x78, 
	0x2a, 0x0b, 0x32, 0x9c, 0x5a, 0x4d, 0x8c, 0x26, 
	0x20, 0x4e, 0x57, 0xa1, 0x08, 0x00, 0x81, 0x40, 
	0x71, 0x4f, 0x81, 0x80, 0x01, 0x01, 0x01, 0x01, 
	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x30, 0x2a, 
	0x00, 0x98, 0x51, 0x00, 0x2a, 0x40, 0x30, 0x70, 
	0x13, 0x00, 0x52, 0x0e, 0x11, 0x00, 0x00, 0x1e, 
	0x00, 0x00, 0x00, 0xfc, 0x00, 0x4c, 0x43, 0x44, 
	0x20, 0x31, 0x37, 0x44, 0x0a, 0x20, 0x20, 0x20, 
	0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x3c, 
	0x3c, 0x1f, 0x40, 0x0b, 0x00, 0x0a, 0x20, 0x20, 
	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xff, 
	0x00, 0x57, 0x43, 0x43, 0x45, 0x31, 0x34, 0x30, 
	0x33, 0x32, 0x33, 0x36, 0x0a, 0x20, 0x00, 0xd8, 
};

/* CEA 861C subset of all EMhwlib video modes */
enum EMhwlibTVStandard cea861c[] = {
	EMhwlibTVStandard_HDMI_640x480p60, // 1
	EMhwlibTVStandard_HDMI_480p60, // 2
	EMhwlibTVStandard_HDMI_480p60, // 3
	EMhwlibTVStandard_HDMI_720p60, // 4
	EMhwlibTVStandard_HDMI_1080i60, // 5
	EMhwlibTVStandard_HDMI_480i60, // 6
	EMhwlibTVStandard_HDMI_480i60, // 7
	EMhwlibTVStandard_HDMI_240p60, // 8
	EMhwlibTVStandard_HDMI_240p60, // 9
	EMhwlibTVStandard_HDMI_2880x480i60, // 10
	EMhwlibTVStandard_HDMI_2880x480i60, // 11
	EMhwlibTVStandard_HDMI_2880x240p60, // 12
	EMhwlibTVStandard_HDMI_2880x240p60, // 13
	EMhwlibTVStandard_HDMI_1440x480p60, // 14
	EMhwlibTVStandard_HDMI_1440x480p60, // 15
	EMhwlibTVStandard_HDMI_1080p60, // 16
	EMhwlibTVStandard_HDMI_576p50, // 17
	EMhwlibTVStandard_HDMI_576p50, // 18
	EMhwlibTVStandard_HDMI_720p50, // 19
	EMhwlibTVStandard_HDMI_1080i50, // 20
	EMhwlibTVStandard_HDMI_576i50, // 21
	EMhwlibTVStandard_HDMI_576i50, // 22
	EMhwlibTVStandard_HDMI_288p50, // 23
	EMhwlibTVStandard_HDMI_288p50, // 24
	EMhwlibTVStandard_HDMI_2880x576i50, // 25
	EMhwlibTVStandard_HDMI_2880x576i50, // 26
	EMhwlibTVStandard_HDMI_2880x288p50, // 27
	EMhwlibTVStandard_HDMI_2880x288p50, // 28
	EMhwlibTVStandard_HDMI_1440x576p50, // 29
	EMhwlibTVStandard_HDMI_1440x576p50, // 30