msp4450g.c

Sample code for use on smp 863x processor.

#include "msp4450g.h"
#include "i2c.h"
#define DMSG 1
#define MPRINT(x) { DMSG ?printf x:0; }

#define MSP4450G_I2C_ADDR			0x80 >> 1
#define MSP4450G_SADDR_CONTROL		0x00
#define MSP4450G_SADDR_WRDEMOD		0x10
#define	MSP4450G_SADDR_RDDEMOD		0x11
#define MSP4450G_SADDR_WRDSP		0x12
#define	MSP4450G_SADDR_RDDSP		0x13
#define MSP4450G_DELAY				10

#define I2S_srcIN_PRESCALE	0x11
#define MSPSI2S_PRESCALE_OFF	0x00
#define MSPSI2S_PRESCALE_0DB	0x10
#define MSPSI2S_PRESCALE_14DB	0x7f

typedef enum { 
	msp_dmreg_standardselect=0x0020, 
		msp_dmreg_modus=0x0030, 
		msp_dmreg_i2sconfig=0x0040,
		msp_dmreg_standardresult=0x007E, 
		msp_dmreg_status = 0x0200 
} MSP4450G_DEMOD_REGISTER;

static RMstatus msp4450g_readDsp(struct RUA *pInstance,
						  RMuint32 regAddr,
						  RMuint32 *regValue)
{
	RMstatus err=RM_OK;
	err=read_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_RDDSP,regAddr,regValue);
	return err;
}

RMstatus msp4450g_detect(struct RUA *pInstance)
{
	RMstatus s=RM_OK;
	RMuint32 regValue=0;
	
	if( msp4450g_readDsp(pInstance,0x001E, &regValue) != RM_OK )
	{
		printf("msp4450g_detect() error <1> \n ") ;
		return RM_NOT_FOUND;
	}
	
	if( regValue != 0x0317 )
	{
		printf("msp4450g_detect() error <2> reg 0x1e = 0x%lx \n",regValue) ;
		return RM_NOT_FOUND;
	}
	
	s = msp4450g_readDsp(pInstance, 0x001F, &regValue);
	return s;
}



static RMstatus msp4450g_writeControl(struct RUA *pInstance,RMuint16 data)
{
	RMstatus err=RM_OK;
	err=write_i2c_control_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_CONTROL, data);	
	return err;
}

RMstatus msp4450g_reset(struct RUA *pInstance)
{
	RMstatus err=RM_OK;
	if( msp4450g_writeControl(pInstance, 0x8000) != RM_OK )
	{
		printf("msp4450g_reset() error <1>\n");
		return RM_ERROR;
	}	
	 err=msp4450g_writeControl(pInstance,0x0000);
	 return err;
}

static RMstatus msp4450g_writeDemod(struct RUA *pInstance, RMuint32 regAddr, RMuint32 data)
{
	return write_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR, MSP4450G_SADDR_WRDEMOD, regAddr, data);
}


RMstatus msp4450g_demod_selectStandard(struct RUA *pInstance, MSP4450G_STANDARD s)
{
	
	if( msp4450g_writeDemod(pInstance, 0x0020, s) != RM_OK )
		return RM_ERROR;
	
	return RM_OK;
}


RMstatus msp4450g_demod_InputFMamPrescale(struct RUA *pInstance,MSP4450G_FMamPRESCALE p)
{
	RMuint32 uCfg=0x00;
	RMuint32 regValue=0x00;
	RMstatus s;
	
//	assert( pC != NULL);
	
	switch( p )
	{
	case msp_fm28khz:
		uCfg = 0x7F00;
		break;
	case msp_fm50khz:
		uCfg = 0x4800;
		break;
	case msp_fm75khz:
		uCfg = 0x3000;
		break;
	case msp_fm100khz:
		uCfg = 0x2400;
		break;
	case msp_fm150khz:
		uCfg = 0x1800;
		break;
	case msp_fm180khz:
		uCfg = 0x1300;
		break;
		
	case msp_fm_hdev2_150khz:
		uCfg = 0x3000;
		break;
	case msp_fm_hdev2_360khz:
		uCfg = 0x1400;
		break;
		
	case msp_fm_hdev3_450khz:
		uCfg = 0x2000;
		break;
	case msp_fm_hdev3_540khz:
		uCfg = 0x1A00;
		break;
		
	case msp_fm_satellite:
		uCfg = 0x1000;
		break;
		
	case msp_am:
		uCfg = 0x7C00;
		break;
		
	default:
		return RM_INVALID_PARAMETER;
		break;
	}
	
	if( (s = read_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_RDDSP,0x000e, &regValue)) != RM_OK )
	{
		printf("msp4450g_demod_InputFMamPrescale, msp4450g_readDsp() failed %d\n", s);
		return RM_ERROR;
	}
	
	// cfg is bit 15:8
	regValue = (regValue & 0xFF) | uCfg; //
	
/*
	data16 = 0x0002;
	data16 = (data16 & 0xFF) | uCfg; // YVo add
*/
	
	if( (s = write_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_WRDSP, 0x0e, regValue)) != RM_OK )
	{
		printf("msp4450g_demod_InputFMamPrescale, msp4450g_writeDsp(data=0x%lx) failed %d\n", regValue, s);
		return RM_ERROR;
	}
	
	return RM_OK;
}

RMstatus msp4450g_demod_getDetectedStandard(struct RUA *pInstance, RMuint32 *regValue)
{

	if( read_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_RDDEMOD,0x007e, regValue) != RM_OK )
		return RM_ERROR;
	
	return RM_OK;
}


RMstatus msp4450g_demod_init(struct RUA *pInstance,  MSP4450G_DETECT_45MHZ nD45mhz, MSP4450G_DETECT_65MHZ nD65mhz, 
							 MSP4450G_DIGIO_MODE digIOMode, RMuint32 i2sMode)
{
	RMuint16 data16;

	// [0] = 1, automatic sound select ON
	data16 = 0x0001;
	
	// [15] = 0
	// [14:13] 4.5 mhz carrier
	switch( nD45mhz )
	{
	case msp_45mhz_MKorea:
		break;
	case msp_45mhz_MBtsc:
		
		data16 = data16 | (0x01 << 13);
		break;
	case msp_45mhz_MJapan:
		data16 = data16 | (0x02 << 13);
		break;
	case msp_45mhz_ChromaCarrier:
		data16 = data16 | (0x03 << 13);
		break;
	
	default:
		return RM_INVALID_PARAMETER;
		break;
	}
	
	// [12] 6.5Mhz carrier
	switch( nD65mhz )
	{
	case msp_65mhz_LSecam:
		break;
	case msp_65mhz_DK123Nicam:
		data16 = data16 | (0x01 << 12);
		break;
		
	default:
		return RM_INVALID_PARAMETER;
		break;
	}
	

	
	switch( digIOMode )
	{
	case msp_digio_outputenable:
		// [3] = 0;
		break;
	
	case msp_digio_tristate:
		data16 = data16 | 0x0008;
		break;
			
	case msp_digio_out_and_interrupt:
		// [3] = 0;
		// [1] = 1;
		data16 = data16 | 0x0002;
		break;
		
	default:
		printf("msp4450g_init() digIOMode %d invalid\n", digIOMode);
		return RM_INVALID_PARAMETER;
		break;
	}

	
	
	// no extra options...
	//assert( (i2sMode & ~(MSP4450G_I2SOUT_PIN_TRISTATE | MSP4450G_I2SOUT_MODE_SLAVE |MSP4450G_I2SOUT_STROBEWS_1CLK | MSP4450G_I2SOUT_BIT_32)) == 0 );
	// zero out lsb, it is taken care of in another register.
	data16 = data16 | (i2sMode & (~MSP4450G_I2SOUT_BIT_32));

	
	// <1> (typcal configuration, not below)
	// 0 01(4.5mhz=btsc) 0(6.5mhz=SECAM) 0000 0(AUD_CL_OUT=X) 0(I2S STRBalign) 0(I2S master) 0(I2S=X) 
	// 0(Dig IO=active for Test Point) 0 1(DigIO Status) 1(Automatic Sound Sel)
	// = 0x2003

	//data16 = data16 & 0xFFF7;
	//data16 = data16 & 0xFFFE;
	//data16 = data16 | 0x18;
	//data16 = data16 & 0xFFE7;//3,4 Audio_2
	
	
		
	if( write_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_WRDEMOD,0x30, data16) != RM_OK )
	{
		printf("msp4450g_init() writeDemod(modus) failed\n");
		return RM_ERROR;
	}
	
	//return RM_OK;
	
	if( i2sMode & MSP4450G_I2SOUT_BIT_32 )
	{
		data16 = 0x0001;
	}
	else
	{
		data16 = 0x0000;
	}
	
	if( write_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_WRDEMOD,0x30, data16) != RM_OK )
	{
		printf("msp4450g_i2sout_configure() writeDemod(i2sconfig, 0x%x) failed\n", data16);
		return RM_ERROR;
	}
	
	return RM_OK;
}

//
//Input: SCART1 DSP
//-------------------------------------------------------------------------------
RMstatus msp4450g_scartdsp_SelectSource(struct RUA *pInstance, MSP4450G_SC_DSP_SRC src)
{
	RMuint32 data16;
	RMstatus s;
	
	s = read_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_RDDSP,0x0013, &data16);

	if( s != RM_OK )
	{
		printf("msp4450g_scart1dsp_SelectSource, msp4450g_readDsp(msp_dsreg_acbreg) failed %d\n", s);
		return RM_ERROR;
	}
	
	//  bit    5432 1098 7854 3210
	//  mask = 1111 1100 1101 1111
	//           xx xx00 xx0      
	//  sc_dsp_src_monoin= 0000 1000
	//  shift 5 to match bits
	data16 = data16 & 0xFCDF;
	data16 = data16 | (src << 5);
	
	s = write_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_WRDSP,0x0013, data16);
	if( s != RM_OK )
	{
		printf("msp4450g_scart1dsp_SelectSource, msp4450g_writeDsp(msp_dsreg_acbreg, data=0x%lx) failed %d\n", data16, s);
		return RM_ERROR;
	}
	
	return RM_OK;

}

RMstatus msp4450g_scartdsp_InputPrescale(struct RUA *pInstance,RMuint32 db)
{
	RMuint32 data16;
	RMstatus s;
	
	if( db > 0x7f)
		return RM_INVALID_PARAMETER;
	
	
	data16 = db << 8;	
	
	if( (s = write_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_WRDSP,0x000d, data16)) != RM_OK )
	{
		printf("msp4450g_scart1dsp_InputPrescale, msp4450g_writeDsp(msp_dsreg_scartdsp_prescale, data=0x%lx) failed %d\n", data16, s);
		return RM_ERROR;
	}
	
	return RM_OK;
}


RMstatus msp4450g_matrix_SelectMode(struct RUA *pInstance, MSP4450G_MATRIX m, MSP4450G_MATRIX_MODE md)
{
	RMuint32 data16;
	RMstatus s;
	
//	assert( pC != NULL );
	
	switch( m )
	{
	case matrix_main:
		//khuong add
	case matrix_headphone:
		//khuong end
	case matrix_sc1DA:
	case matrix_i2s:
	case matrix_qpeak:
		
		break;
	default:
		return RM_INVALID_PARAMETER;
	}
	
	switch( md )
	{
	case matrix_mode_soundAMono:
	case matrix_mode_soundBMono:
	case matrix_mode_stereo:
	case matrix_mode_mono:
	case matrix_mode_sumDiff:
	case matrix_mode_abXchange:
	case matrix_mode_phaseChangeB:
	case matrix_mode_phaseChangeA:
	case matrix_mode_onlyA:
	case matrix_mode_onlyB:
		break;
	default:
		return RM_INVALID_PARAMETER;
	}
	
	if( (s = read_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_RDDSP,m, &data16)) != RM_OK )
	{
		printf("msp4450g_matrix_SelectSource, msp4450g_readDsp(0x%x) failed %d\n", m, s);
		return RM_ERROR;
	}
	
	// source is bit 15:8
	data16 = data16 & 0xFF00;
	data16 = data16 | md;
	if( (s = write_i2c_dsp_msp4450g(pInstance,MSP4450G_DELAY,MSP4450G_I2C_ADDR,MSP4450G_SADDR_WRDSP,m, data16)) != RM_OK )
	{
		printf("msp4450g_matrix_SelectSource, msp4450g_writeDsp(0x%x, data=0x%lx) failed %d\n", m, data16, s);
		return RM_ERROR;
	}
	
	return RM_OK;	
	
}



//
// MATRIX Operations
//-------------------------------------------------------------------------------
RMstatus msp4450g_matrix_SelectSource(struct RUA *pInstance, MSP4450G_MATRIX m, MSP4450G_MATRIX_SRC src)
{
	RMuint32 data16;
	RMstatus s;
	
	switch( m )
	{
	case matrix_main:
		//khuong add
	case matrix_headphone:	
		//khuong end
	case matrix_sc1DA:
	case matrix_i2s:
	case matrix_qpeak:
		break;
	default:
		return RM_INVALID_PARAMETER;
	}
	
	switch( src )
	{
	case matrix_src_demodFMAM:
	case matrix_src_stereoAB:
	case matrix_src_stereoA:
	case matrix_src_stereoB:
	case matrix_src_SCARTin: