📄 timing_recovery_1.mdl
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Annotation {
Name "Filter Coefficients from Chris Dick Xilinx, \nor H. Meyer pp 520 (9-33) Digital Communications Rec"
"eivers"
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Name "I/Q Data"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
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BlockType Reference
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SourceBlock "dspsigops/Delay"
SourceType "Delay"
dly_unit "Samples"
delay "2"
ic_detail off
dif_ic_for_ch off
dif_ic_for_dly off
ic "0"
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BlockType Reference
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h "rrc_coef"
D "2"
filtStruct "Direct form"
framing "Maintain input frame size"
outputBufInitCond "0"
additionalParams off
allowOverrides on
firstCoeffMode "Same word length as input"
firstCoeffWordLength "16"
firstCoeffFracLength "15"
outputMode "Same as accumulator"
outputWordLength "16"
outputFracLength "15"
accumMode "Inherit via internal rule"
accumWordLength "32"
accumFracLength "30"
prodOutputMode "Inherit via internal rule"
prodOutputWordLength "32"
prodOutputFracLength "30"
roundingMode "Floor"
overflowMode off
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ListType AxesTitles
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axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
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TimeRange "2e-006"
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YMax "1.1~1.1~1.5"
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SampleTime "0"
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BlockType Reference
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Position [145, 50, 175, 80]
BackgroundColor "yellow"
SourceBlock "simulink/Math\nOperations/Slider\nGain"
SourceType "Slider Gain"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
low "-1.5"
gain "0"
high "1.5"
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BlockType SubSystem
Name "Symbol Sampling with\nOptional Carrier Recovery"
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Position [450, 380, 555, 480]
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PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
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RequestExecContextInheritance off
MaskHideContents off
System {
Name "Symbol Sampling with\nOptional Carrier Recovery"
Location [133, 288, 668, 580]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
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BlockType Inport
Name "Symbol Clock"
Position [25, 38, 55, 52]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
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Block {
BlockType Inport
Name "Data"
Position [25, 98, 55, 112]
Port "2"
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
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Block {
BlockType Inport
Name "Rec_ON"
Position [65, 123, 95, 137]
Port "3"
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
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Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [115, 29, 150, 61]
SourceBlock "dspsigops/Delay"
SourceType "Delay"
dly_unit "Samples"
delay "2"
ic_detail off
dif_ic_for_ch off
dif_ic_for_dly off
ic "0"
reset_popup "None"
}
Block {
BlockType SubSystem
Name "Symbol Sampler1"
Ports [2, 1, 1]
Position [150, 90, 315, 145]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
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RTWSystemCode "Auto"
FunctionWithSeparateData off
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System {
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Location [31, 286, 569, 551]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
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PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
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BlockType Inport
Name "In1"
Position [45, 198, 75, 212]
IconDisplay "Port number"
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