📄 timing_recovery_2q.mdl
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DstPort 1
}
}
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Filter coefficients"
DstPort 1
}
Line {
SrcBlock "Filter coefficients"
SrcPort 1
DstBlock "Demux"
DstPort 1
}
Line {
SrcBlock "P2"
SrcPort 1
DstBlock "Sum2"
DstPort 1
}
Line {
SrcBlock "P3"
SrcPort 1
DstBlock "Sum3"
DstPort 1
}
Annotation {
Name "Filter Coefficients from Chris Dick Xilinx, \nor H. Meyer pp 520 (9-33) Digital Communications Receivers"
Position [157, 201]
}
Annotation {
Name "Horner's Rule"
Position [348, 18]
}
}
}
Block {
BlockType Outport
Name "Yout"
Position [405, 118, 435, 132]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Line {
SrcBlock "MADS"
SrcPort 1
DstBlock "Yout"
DstPort 1
}
Line {
SrcBlock "Mu"
SrcPort 1
DstBlock "MADS"
DstPort 2
}
Line {
SrcBlock "Xin"
SrcPort 1
DstBlock "Filter State"
DstPort 1
}
Line {
SrcBlock "Filter State"
SrcPort 1
DstBlock "MADS"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "RRC Filter1"
Ports [1, 1]
Position [600, 118, 685, 172]
DialogController "dspdialog.DigitalFilter"
DialogControllerArgs "DataTag0"
SourceBlock "dsparch4/Digital Filter"
SourceType "Digital Filter"
TypePopup "FIR (all zeros)"
IIRFiltStruct "Direct form II transposed"
AllPoleFiltStruct "Direct form"
FIRFiltStruct "Direct form"
CoeffSource "Specify via dialog"
NumCoeffs "rrc_coef"
DenCoeffs "[1 0.1]"
BiQuadCoeffs "[1 0.3 0.4 1 0.1 0.2]"
LatticeCoeffs "[0.2 0.4]"
denIgnore "on"
FiltPerSampPopup "One filter per frame"
IC "0"
ICnum "0"
ICden "0"
additionalParams "off"
allowOverrides "on"
showCoeff "off"
firstCoeffMode "Same word length as input"
firstCoeffWordLength "16"
firstCoeffFracLength "15"
secondCoeffMode "Same as numerator"
secondCoeffWordLength "16"
secondCoeffFracLength "15"
thirdCoeffMode "Same as input"
thirdCoeffWordLength "16"
thirdCoeffFracLength "15"
showOut "off"
outputMode "Same as accumulator"
outputWordLength "16"
outputFracLength "15"
showAcc "off"
accumMode "Same as product output"
accumWordLength "32"
accumFracLength "30"
showMpy "off"
prodOutputMode "Same as input"
prodOutputWordLength "32"
prodOutputFracLength "30"
showMem "off"
memoryMode "Same as accumulator"
memoryWordLength "16"
memoryFracLength "15"
roundingMode "Floor"
overflowMode "off"
ScaleValues "1"
scaleValueFracLength "14"
tapSumMode "Same as input"
tapSumWordLength "32"
tapSumFracLength "30"
stageIOMode "Same as input"
stageIOWordLength "16"
stageInFracLength "15"
stageOutFracLength "15"
LockScale "off"
FilterSource "Specify via dialog"
dfiltObjectName "dfilt.dffir([1 2 1])"
multiplicandMode "Same as output"
multiplicandWordLength "32"
multiplicandFracLength "30"
}
Block {
BlockType SubSystem
Name "Symbol Gen"
Ports [0, 1, 1]
Position [310, 93, 410, 157]
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "Symbol Gen"
Location [94, 225, 616, 455]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [385, 120, 405, 140]
}
Block {
BlockType Gain
Name "Gain for interpolation"
Position [345, 40, 375, 70]
Gain "D*sqrt(2)"
ParameterDataTypeMode "Inherit via internal rule"
ParameterDataType "sfix(16)"
ParameterScaling "2^0"
ParamDataTypeStr "Inherit: Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
OutDataType "sfix(16)"
OutScaling "2^0"
OutDataTypeStr "Inherit: Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "QPSK\nModulator\nBaseband"
Ports [1, 1]
Position [200, 31, 275, 79]
SourceBlock "commdigbbndpm3/QPSK\nModulator\nBaseband"
SourceType "QPSK Modulator Baseband"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
InType "Integer"
Enc "Binary"
Ph "pi/4"
outDtype "double"
outWordLen "16"
outUDDataType "sfix(16)"
outFracLenMode "Best precision"
outFracLen "15"
}
Block {
BlockType Reference
Name "Random Integer\nGenerator"
Ports [0, 1]
Position [55, 33, 135, 77]
FontName "Arial"
SourceBlock "commrandsrc2/Random Integer\nGenerator"
SourceType "Random Integer Generator"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
mul "4"
seed "37"
Ts "-1"
frameBased "off"
sampPerFrame "1"
orient "off"
outDataType "double"
}
Block {
BlockType Outport
Name "Out"
Position [440, 48, 470, 62]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
OutputWhenDisabled "reset"
InitialOutput "0+j*eps"
}
Line {
SrcBlock "Gain for interpolation"
SrcPort 1
DstBlock "Out"
DstPort 1
}
Line {
SrcBlock "Random Integer\nGenerator"
SrcPort 1
DstBlock "QPSK\nModulator\nBaseband"
DstPort 1
}
Line {
SrcBlock "QPSK\nModulator\nBaseband"
SrcPort 1
DstBlock "Gain for interpolation"
DstPort 1
}
Annotation {
Name "NOTE: The output PORT is set to ZERO\nwhen this subsyem is NOT enabled. \nThis effectivly inserts "
"Zeros into the data stream\n for proper interpolation. "
Position [229, 162]
}
}
}
Block {
BlockType SubSystem
Name "Timing Control Unit"
Ports [1, 2]
Position [130, 48, 225, 117]
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "Timing Control Unit"
Location [55, 382, 954, 646]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "Control In"
Position [25, 98, 55, 112]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Reference
Name "Delay2"
Ports [1, 1]
Position [195, 88, 250, 122]
SourceBlock "dspsigops/Delay"
SourceType "Delay"
dly_unit "Samples"
delay "1"
ic_detail "on"
dif_ic_for_ch "off"
dif_ic_for_dly "off"
ic "0"
reset_popup "None"
}
Block {
BlockType Reference
Name "Discrete\nConstant1"
Ports [0, 1]
Position [205, 144, 235, 176]
ShowName off
SourceBlock "dspsrcs4/DSP\nConstant"
SourceType "DSP Constant"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Value "1"
SampleMode "Discrete"
discreteOutput "Sample-based (interpret vectors as 1-D)"
continuousOutput "Sample-based"
sampTime "1/(D*Fsymbol)"
framePeriod "1/(D*Fsymbol)"
additionalParams "on"
allowOverrides "on"
dataType "Inherit via back propagation"
isSigned "on"
wordLen "16"
udDataType "sfix(16)"
fracBitsMode "Best precision"
numFracBits "15"
InterpretAs1D "on"
Ts "1/(D*Fsymbol)"
FramebasedOutput "off"
}
Block {
BlockType Reference
Name "Discrete\nConstant3"
Ports [0, 1]
Position [25, 48, 65, 82]
ShowName off
SourceBlock "dspsrcs4/DSP\nConstant"
SourceType "DSP Constant"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Value "1/D"
SampleMode "Discrete"
discreteOutput "Sample-based (interpret vectors as 1-D)"
continuousOutput "Sample-based"
sampTime " 1/(D*Fsymbol)"
framePeriod " 1/(D*Fsymbol)"
additionalParams "on"
allowOverrides "on"
dataType "Inherit via back propagation"
isSigned "on"
wordLen "16"
udDataType "sfix(16)"
fracBitsMode "Best precision"
numFracBits "15"
InterpretAs1D "on"
Ts " 1/(D*Fsymbol)"
FramebasedOutput "off"
}
Block {
BlockType Math
Name "Math\nFunction"
Ports [2, 1]
Position [345, 97, 375, 128]
Operator "mod"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType RelationalOperator
Name "Relational\nOperator1"
Position [435, 47, 465, 78]
Operator "<"
InputSameDT off
LogicOutDataTypeMode "boolean"
LogicDataType "double(64)"
OutDataTypeStr "boolean"
}
Block {
BlockType SubSystem
Name "S&H 1"
Ports [1, 1, 1]
Position [480, 172, 565, 228]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "S&H 1"
Location [251, 416, 573, 620]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [55, 48, 85, 62]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [150, 70, 170, 90]
}
Block {
BlockType Outport
Name "Out1"
Position [255, 48, 285, 62]
IconDisplay "Port number"
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