test.fit.rpt

switch code,for thinx cpld

; sw1[7]  ; Input    ; 0             ;
; sw1[6]  ; Input    ; 0             ;
; sw1[5]  ; Input    ; 0             ;
; sw1[4]  ; Input    ; 0             ;
; sw1[3]  ; Input    ; 0             ;
; sw1[2]  ; Input    ; 0             ;
; sw1[1]  ; Input    ; 0             ;
; sw1[0]  ; Input    ; 0             ;
; led1[7] ; Output   ; --            ;
; led1[6] ; Output   ; --            ;
; led1[5] ; Output   ; --            ;
; led1[4] ; Output   ; --            ;
; led1[3] ; Output   ; --            ;
; led1[2] ; Output   ; --            ;
; led1[1] ; Output   ; --            ;
; led1[0] ; Output   ; --            ;
+---------+----------+---------------+


+---------------------------------+
; Non-Global High Fan-Out Signals ;
+--------+------------------------+
; Name   ; Fan-Out                ;
+--------+------------------------+
; sw1[0] ; 1                      ;
; sw1[1] ; 1                      ;
; sw1[2] ; 1                      ;
; sw1[3] ; 1                      ;
; sw1[4] ; 1                      ;
; sw1[5] ; 1                      ;
; sw1[6] ; 1                      ;
; sw1[7] ; 1                      ;
+--------+------------------------+


+---------------------------------------------------+
; Interconnect Usage Summary                        ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage                ;
+----------------------------+----------------------+
; C4s                        ; 16 / 2,870 ( < 1 % ) ;
; Direct links               ; 0 / 3,938 ( 0 % )    ;
; Global clocks              ; 0 / 4 ( 0 % )        ;
; LAB clocks                 ; 0 / 72 ( 0 % )       ;
; LUT chains                 ; 0 / 1,143 ( 0 % )    ;
; Local interconnects        ; 8 / 3,938 ( < 1 % )  ;
; R4s                        ; 16 / 2,832 ( < 1 % ) ;
+----------------------------+----------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Thu Jun 26 11:35:17 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off test -c test
Info: Selected device EPM1270T144C5 for design "test"
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM570T144A5 is compatible
    Info: Device EPM1270T144I5 is compatible
    Info: Device EPM1270T144A5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is pin to pin delay of 7.419 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_37; Fanout = 1; PIN Node = 'sw1[3]'
    Info: 2: + IC(3.965 ns) + CELL(2.322 ns) = 7.419 ns; Loc. = PIN_127; Fanout = 0; PIN Node = 'led1[3]'
    Info: Total cell delay = 3.454 ns ( 46.56 % )
    Info: Total interconnect delay = 3.965 ns ( 53.44 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
    Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file F:/[Studio]/CPLD Competition/光盘/例程/switch/test.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 167 megabytes of memory during processing
    Info: Processing ended: Thu Jun 26 11:35:18 2008
    Info: Elapsed time: 00:00:01


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/[Studio]/CPLD Competition/光盘/例程/switch/test.fit.smsg.