song.map.qmsg

speaker code,for thinx cpld

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 26 11:38:35 2008 " "Info: Processing started: Thu Jun 26 11:38:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off block1 -c song " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off block1 -c song" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdiv6.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clockdiv6.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clockdiv6-behavioural " "Info: Found design unit 1: clockdiv6-behavioural" {  } { { "clockdiv6.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/clockdiv6.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clockdiv6 " "Info: Found entity 1: clockdiv6" {  } { { "clockdiv6.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/clockdiv6.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdiv4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clockdiv4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clockdiv4-behavioural " "Info: Found design unit 1: clockdiv4-behavioural" {  } { { "clockdiv4.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/clockdiv4.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clockdiv4 " "Info: Found entity 1: clockdiv4" {  } { { "clockdiv4.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/clockdiv4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "song.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file song.v" { { "Info" "ISGN_ENTITY_NAME" "1 song " "Info: Found entity 1: song" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "Block1 " "Warning: Processing legacy GDF or BDF entity \"Block1\" with Max+Plus II bus and instance naming rules" {  } { { "Block1.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "song song:inst " "Info: Elaborating entity \"song\" for hierarchy \"song:inst\"" {  } { { "Block1.bdf" "inst" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { { 120 512 648 216 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 song.v(16) " "Warning (10230): Verilog HDL assignment warning at song.v(16): truncated value with size 32 to match size of target (14)" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 song.v(44) " "Warning (10230): Verilog HDL assignment warning at song.v(44): truncated value with size 32 to match size of target (8)" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 44 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clockdiv6 clockdiv6:inst2 " "Info: Elaborating entity \"clockdiv6\" for hierarchy \"clockdiv6:inst2\"" {  } { { "Block1.bdf" "inst2" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { { 56 312 440 152 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clockdiv4 clockdiv4:inst1 " "Info: Elaborating entity \"clockdiv4\" for hierarchy \"clockdiv4:inst1\"" {  } { { "Block1.bdf" "inst1" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { { 184 312 440 280 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "song:inst\|med\[3\] data_in GND " "Warning (14130): Reduced register \"song:inst\|med\[3\]\" with stuck data_in port to stuck value GND" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 41 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "song:inst\|low\[3\] data_in GND " "Warning (14130): Reduced register \"song:inst\|low\[3\]\" with stuck data_in port to stuck value GND" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 41 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "song:inst\|high\[1\] data_in GND " "Warning (14130): Reduced register \"song:inst\|high\[1\]\" with stuck data_in port to stuck value GND" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 41 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "song:inst\|high\[2\] data_in GND " "Warning (14130): Reduced register \"song:inst\|high\[2\]\" with stuck data_in port to stuck value GND" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 41 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "song:inst\|high\[3\] data_in GND " "Warning (14130): Reduced register \"song:inst\|high\[3\]\" with stuck data_in port to stuck value GND" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 41 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "178 " "Info: Implemented 178 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "176 " "Info: Implemented 176 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "161 " "Info: Allocated 161 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 26 11:38:39 2008 " "Info: Processing ended: Thu Jun 26 11:38:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}