song.tan.qmsg

speaker code,for thinx cpld

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "song:inst\|speaker song:inst\|speaker clk 9 ps " "Info: Found hold time violation between source  pin or register \"song:inst\|speaker\" and destination pin or register \"song:inst\|speaker\" for clock \"clk\" (Hold time is 9 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.658 ns + Largest " "Info: + Largest clock skew is 1.658 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.015 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 15.015 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 27; CLK Node = 'clk'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { { 152 48 216 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv6:inst2\|clock_int 2 REG LC_X13_Y3_N2 15 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X13_Y3_N2; Fanout = 15; REG Node = 'clockdiv6:inst2\|clock_int'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv6:inst2|clock_int } "NODE_NAME" } } { "clockdiv6.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/clockdiv6.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.516 ns) + CELL(1.294 ns) 9.005 ns song:inst\|divider\[7\] 3 REG LC_X11_Y9_N0 4 " "Info: 3: + IC(3.516 ns) + CELL(1.294 ns) = 9.005 ns; Loc. = LC_X11_Y9_N0; Fanout = 4; REG Node = 'song:inst\|divider\[7\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.810 ns" { clockdiv6:inst2|clock_int song:inst|divider[7] } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.047 ns) + CELL(0.914 ns) 11.966 ns song:inst\|Equal0~164 4 COMB LC_X9_Y9_N9 1 " "Info: 4: + IC(2.047 ns) + CELL(0.914 ns) = 11.966 ns; Loc. = LC_X9_Y9_N9; Fanout = 1; COMB Node = 'song:inst\|Equal0~164'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.961 ns" { song:inst|divider[7] song:inst|Equal0~164 } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.718 ns) + CELL(0.740 ns) 13.424 ns song:inst\|Equal0 5 COMB LC_X9_Y9_N6 15 " "Info: 5: + IC(0.718 ns) + CELL(0.740 ns) = 13.424 ns; Loc. = LC_X9_Y9_N6; Fanout = 15; COMB Node = 'song:inst\|Equal0'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.458 ns" { song:inst|Equal0~164 song:inst|Equal0 } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.918 ns) 15.015 ns song:inst\|speaker 6 REG LC_X9_Y9_N2 2 " "Info: 6: + IC(0.673 ns) + CELL(0.918 ns) = 15.015 ns; Loc. = LC_X9_Y9_N2; Fanout = 2; REG Node = 'song:inst\|speaker'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { song:inst|Equal0 song:inst|speaker } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.323 ns ( 42.11 % ) " "Info: Total cell delay = 6.323 ns ( 42.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.692 ns ( 57.89 % ) " "Info: Total interconnect delay = 8.692 ns ( 57.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.015 ns" { clk clockdiv6:inst2|clock_int song:inst|divider[7] song:inst|Equal0~164 song:inst|Equal0 song:inst|speaker } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "15.015 ns" { clk {} clk~combout {} clockdiv6:inst2|clock_int {} song:inst|divider[7] {} song:inst|Equal0~164 {} song:inst|Equal0 {} song:inst|speaker {} } { 0.000ns 0.000ns 1.738ns 3.516ns 2.047ns 0.718ns 0.673ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.914ns 0.740ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.357 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 13.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 27; CLK Node = 'clk'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { { 152 48 216 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv6:inst2\|clock_int 2 REG LC_X13_Y3_N2 15 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X13_Y3_N2; Fanout = 15; REG Node = 'clockdiv6:inst2\|clock_int'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv6:inst2|clock_int } "NODE_NAME" } } { "clockdiv6.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/clockdiv6.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.516 ns) + CELL(1.294 ns) 9.005 ns song:inst\|divider\[9\] 3 REG LC_X11_Y9_N2 4 " "Info: 3: + IC(3.516 ns) + CELL(1.294 ns) = 9.005 ns; Loc. = LC_X11_Y9_N2; Fanout = 4; REG Node = 'song:inst\|divider\[9\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.810 ns" { clockdiv6:inst2|clock_int song:inst|divider[9] } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.056 ns) + CELL(0.200 ns) 11.261 ns song:inst\|Equal0~165 4 COMB LC_X9_Y9_N5 1 " "Info: 4: + IC(2.056 ns) + CELL(0.200 ns) = 11.261 ns; Loc. = LC_X9_Y9_N5; Fanout = 1; COMB Node = 'song:inst\|Equal0~165'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.256 ns" { song:inst|divider[9] song:inst|Equal0~165 } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 11.766 ns song:inst\|Equal0 5 COMB LC_X9_Y9_N6 15 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 11.766 ns; Loc. = LC_X9_Y9_N6; Fanout = 15; COMB Node = 'song:inst\|Equal0'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { song:inst|Equal0~165 song:inst|Equal0 } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.918 ns) 13.357 ns song:inst\|speaker 6 REG LC_X9_Y9_N2 2 " "Info: 6: + IC(0.673 ns) + CELL(0.918 ns) = 13.357 ns; Loc. = LC_X9_Y9_N2; Fanout = 2; REG Node = 'song:inst\|speaker'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { song:inst|Equal0 song:inst|speaker } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.069 ns ( 37.95 % ) " "Info: Total cell delay = 5.069 ns ( 37.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.288 ns ( 62.05 % ) " "Info: Total interconnect delay = 8.288 ns ( 62.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "13.357 ns" { clk clockdiv6:inst2|clock_int song:inst|divider[9] song:inst|Equal0~165 song:inst|Equal0 song:inst|speaker } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "13.357 ns" { clk {} clk~combout {} clockdiv6:inst2|clock_int {} song:inst|divider[9] {} song:inst|Equal0~165 {} song:inst|Equal0 {} song:inst|speaker {} } { 0.000ns 0.000ns 1.738ns 3.516ns 2.056ns 0.305ns 0.673ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.200ns 0.200ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.015 ns" { clk clockdiv6:inst2|clock_int song:inst|divider[7] song:inst|Equal0~164 song:inst|Equal0 song:inst|speaker } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "15.015 ns" { clk {} clk~combout {} clockdiv6:inst2|clock_int {} song:inst|divider[7] {} song:inst|Equal0~164 {} song:inst|Equal0 {} song:inst|speaker {} } { 0.000ns 0.000ns 1.738ns 3.516ns 2.047ns 0.718ns 0.673ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.914ns 0.740ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "13.357 ns" { clk clockdiv6:inst2|clock_int song:inst|divider[9] song:inst|Equal0~165 song:inst|Equal0 song:inst|speaker } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "13.357 ns" { clk {} clk~combout {} clockdiv6:inst2|clock_int {} song:inst|divider[9] {} song:inst|Equal0~165 {} song:inst|Equal0 {} song:inst|speaker {} } { 0.000ns 0.000ns 1.738ns 3.516ns 2.056ns 0.305ns 0.673ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.200ns 0.200ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 3 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.494 ns - Shortest register register " "Info: - Shortest register to register delay is 1.494 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns song:inst\|speaker 1 REG LC_X9_Y9_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y9_N2; Fanout = 2; REG Node = 'song:inst\|speaker'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { song:inst|speaker } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.903 ns) + CELL(0.591 ns) 1.494 ns song:inst\|speaker 2 REG LC_X9_Y9_N2 2 " "Info: 2: + IC(0.903 ns) + CELL(0.591 ns) = 1.494 ns; Loc. = LC_X9_Y9_N2; Fanout = 2; REG Node = 'song:inst\|speaker'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { song:inst|speaker song:inst|speaker } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.591 ns ( 39.56 % ) " "Info: Total cell delay = 0.591 ns ( 39.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.903 ns ( 60.44 % ) " "Info: Total interconnect delay = 0.903 ns ( 60.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { song:inst|speaker song:inst|speaker } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "1.494 ns" { song:inst|speaker {} song:inst|speaker {} } { 0.000ns 0.903ns } { 0.000ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 3 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.015 ns" { clk clockdiv6:inst2|clock_int song:inst|divider[7] song:inst|Equal0~164 song:inst|Equal0 song:inst|speaker } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "15.015 ns" { clk {} clk~combout {} clockdiv6:inst2|clock_int {} song:inst|divider[7] {} song:inst|Equal0~164 {} song:inst|Equal0 {} song:inst|speaker {} } { 0.000ns 0.000ns 1.738ns 3.516ns 2.047ns 0.718ns 0.673ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.914ns 0.740ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "13.357 ns" { clk clockdiv6:inst2|clock_int song:inst|divider[9] song:inst|Equal0~165 song:inst|Equal0 song:inst|speaker } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "13.357 ns" { clk {} clk~combout {} clockdiv6:inst2|clock_int {} song:inst|divider[9] {} song:inst|Equal0~165 {} song:inst|Equal0 {} song:inst|speaker {} } { 0.000ns 0.000ns 1.738ns 3.516ns 2.056ns 0.305ns 0.673ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.200ns 0.200ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { song:inst|speaker song:inst|speaker } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "1.494 ns" { song:inst|speaker {} song:inst|speaker {} } { 0.000ns 0.903ns } { 0.000ns 0.591ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk speak song:inst\|speaker 20.396 ns register " "Info: tco from clock \"clk\" to destination pin \"speak\" through register \"song:inst\|speaker\" is 20.396 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 15.015 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 15.015 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 27; CLK Node = 'clk'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { { 152 48 216 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv6:inst2\|clock_int 2 REG LC_X13_Y3_N2 15 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X13_Y3_N2; Fanout = 15; REG Node = 'clockdiv6:inst2\|clock_int'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv6:inst2|clock_int } "NODE_NAME" } } { "clockdiv6.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/clockdiv6.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.516 ns) + CELL(1.294 ns) 9.005 ns song:inst\|divider\[7\] 3 REG LC_X11_Y9_N0 4 " "Info: 3: + IC(3.516 ns) + CELL(1.294 ns) = 9.005 ns; Loc. = LC_X11_Y9_N0; Fanout = 4; REG Node = 'song:inst\|divider\[7\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.810 ns" { clockdiv6:inst2|clock_int song:inst|divider[7] } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.047 ns) + CELL(0.914 ns) 11.966 ns song:inst\|Equal0~164 4 COMB LC_X9_Y9_N9 1 " "Info: 4: + IC(2.047 ns) + CELL(0.914 ns) = 11.966 ns; Loc. = LC_X9_Y9_N9; Fanout = 1; COMB Node = 'song:inst\|Equal0~164'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.961 ns" { song:inst|divider[7] song:inst|Equal0~164 } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.718 ns) + CELL(0.740 ns) 13.424 ns song:inst\|Equal0 5 COMB LC_X9_Y9_N6 15 " "Info: 5: + IC(0.718 ns) + CELL(0.740 ns) = 13.424 ns; Loc. = LC_X9_Y9_N6; Fanout = 15; COMB Node = 'song:inst\|Equal0'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.458 ns" { song:inst|Equal0~164 song:inst|Equal0 } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.918 ns) 15.015 ns song:inst\|speaker 6 REG LC_X9_Y9_N2 2 " "Info: 6: + IC(0.673 ns) + CELL(0.918 ns) = 15.015 ns; Loc. = LC_X9_Y9_N2; Fanout = 2; REG Node = 'song:inst\|speaker'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { song:inst|Equal0 song:inst|speaker } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.323 ns ( 42.11 % ) " "Info: Total cell delay = 6.323 ns ( 42.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.692 ns ( 57.89 % ) " "Info: Total interconnect delay = 8.692 ns ( 57.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.015 ns" { clk clockdiv6:inst2|clock_int song:inst|divider[7] song:inst|Equal0~164 song:inst|Equal0 song:inst|speaker } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "15.015 ns" { clk {} clk~combout {} clockdiv6:inst2|clock_int {} song:inst|divider[7] {} song:inst|Equal0~164 {} song:inst|Equal0 {} song:inst|speaker {} } { 0.000ns 0.000ns 1.738ns 3.516ns 2.047ns 0.718ns 0.673ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.914ns 0.740ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 3 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.005 ns + Longest register pin " "Info: + Longest register to pin delay is 5.005 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns song:inst\|speaker 1 REG LC_X9_Y9_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y9_N2; Fanout = 2; REG Node = 'song:inst\|speaker'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { song:inst|speaker } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.683 ns) + CELL(2.322 ns) 5.005 ns speak 2 PIN PIN_52 0 " "Info: 2: + IC(2.683 ns) + CELL(2.322 ns) = 5.005 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'speak'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.005 ns" { song:inst|speaker speak } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { { 144 688 864 160 "speak" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 46.39 % ) " "Info: Total cell delay = 2.322 ns ( 46.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.683 ns ( 53.61 % ) " "Info: Total interconnect delay = 2.683 ns ( 53.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.005 ns" { song:inst|speaker speak } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "5.005 ns" { song:inst|speaker {} speak {} } { 0.000ns 2.683ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.015 ns" { clk clockdiv6:inst2|clock_int song:inst|divider[7] song:inst|Equal0~164 song:inst|Equal0 song:inst|speaker } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "15.015 ns" { clk {} clk~combout {} clockdiv6:inst2|clock_int {} song:inst|divider[7] {} song:inst|Equal0~164 {} song:inst|Equal0 {} song:inst|speaker {} } { 0.000ns 0.000ns 1.738ns 3.516ns 2.047ns 0.718ns 0.673ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.914ns 0.740ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.005 ns" { song:inst|speaker speak } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "5.005 ns" { song:inst|speaker {} speak {} } { 0.000ns 2.683ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 26 11:38:46 2008 " "Info: Processing ended: Thu Jun 26 11:38:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}