song.tan.qmsg

speaker code,for thinx cpld

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { { 152 48 216 168 "clk" "" } } } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "20 " "Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clockdiv4:inst1\|clock_int " "Info: Detected ripple clock \"clockdiv4:inst1\|clock_int\" as buffer" {  } { { "clockdiv4.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/clockdiv4.vhd" 22 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clockdiv4:inst1\|clock_int" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[13\] " "Info: Detected ripple clock \"song:inst\|divider\[13\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[12\] " "Info: Detected ripple clock \"song:inst\|divider\[12\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[11\] " "Info: Detected ripple clock \"song:inst\|divider\[11\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[10\] " "Info: Detected ripple clock \"song:inst\|divider\[10\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[9\] " "Info: Detected ripple clock \"song:inst\|divider\[9\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[8\] " "Info: Detected ripple clock \"song:inst\|divider\[8\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[7\] " "Info: Detected ripple clock \"song:inst\|divider\[7\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[6\] " "Info: Detected ripple clock \"song:inst\|divider\[6\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[5\] " "Info: Detected ripple clock \"song:inst\|divider\[5\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[4\] " "Info: Detected ripple clock \"song:inst\|divider\[4\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[3\] " "Info: Detected ripple clock \"song:inst\|divider\[3\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[2\] " "Info: Detected ripple clock \"song:inst\|divider\[2\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[1\] " "Info: Detected ripple clock \"song:inst\|divider\[1\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clockdiv6:inst2\|clock_int " "Info: Detected ripple clock \"clockdiv6:inst2\|clock_int\" as buffer" {  } { { "clockdiv6.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/clockdiv6.vhd" 22 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clockdiv6:inst2\|clock_int" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "song:inst\|Equal0~165 " "Info: Detected gated clock \"song:inst\|Equal0~165\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 11 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|Equal0~165" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "song:inst\|Equal0~166 " "Info: Detected gated clock \"song:inst\|Equal0~166\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 11 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|Equal0~166" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "song:inst\|Equal0~164 " "Info: Detected gated clock \"song:inst\|Equal0~164\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 11 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|Equal0~164" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "song:inst\|Equal0~163 " "Info: Detected gated clock \"song:inst\|Equal0~163\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 11 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|Equal0~163" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "song:inst\|divider\[0\] " "Info: Detected ripple clock \"song:inst\|divider\[0\]\" as buffer" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 13 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "song:inst\|divider\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register song:inst\|med\[1\] register song:inst\|origin\[5\] 81.63 MHz 12.251 ns Internal " "Info: Clock \"clk\" has Internal fmax of 81.63 MHz between source register \"song:inst\|med\[1\]\" and destination register \"song:inst\|origin\[5\]\" (period= 12.251 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.542 ns + Longest register register " "Info: + Longest register to register delay is 11.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns song:inst\|med\[1\] 1 REG LC_X13_Y8_N7 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y8_N7; Fanout = 10; REG Node = 'song:inst\|med\[1\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { song:inst|med[1] } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.283 ns) + CELL(0.740 ns) 2.023 ns song:inst\|Equal1~154 2 COMB LC_X14_Y8_N8 3 " "Info: 2: + IC(1.283 ns) + CELL(0.740 ns) = 2.023 ns; Loc. = LC_X14_Y8_N8; Fanout = 3; COMB Node = 'song:inst\|Equal1~154'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.023 ns" { song:inst|med[1] song:inst|Equal1~154 } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.817 ns) + CELL(0.511 ns) 4.351 ns song:inst\|Equal3~146 3 COMB LC_X12_Y8_N2 3 " "Info: 3: + IC(1.817 ns) + CELL(0.511 ns) = 4.351 ns; Loc. = LC_X12_Y8_N2; Fanout = 3; COMB Node = 'song:inst\|Equal3~146'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.328 ns" { song:inst|Equal1~154 song:inst|Equal3~146 } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.738 ns) + CELL(0.200 ns) 5.289 ns song:inst\|Selector3~164 4 COMB LC_X12_Y8_N0 3 " "Info: 4: + IC(0.738 ns) + CELL(0.200 ns) = 5.289 ns; Loc. = LC_X12_Y8_N0; Fanout = 3; COMB Node = 'song:inst\|Selector3~164'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.938 ns" { song:inst|Equal3~146 song:inst|Selector3~164 } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.511 ns) 6.583 ns song:inst\|WideNor0~75 5 COMB LC_X12_Y8_N6 3 " "Info: 5: + IC(0.783 ns) + CELL(0.511 ns) = 6.583 ns; Loc. = LC_X12_Y8_N6; Fanout = 3; COMB Node = 'song:inst\|WideNor0~75'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.294 ns" { song:inst|Selector3~164 song:inst|WideNor0~75 } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.293 ns) + CELL(0.511 ns) 8.387 ns song:inst\|WideNor0 6 COMB LC_X11_Y8_N0 12 " "Info: 6: + IC(1.293 ns) + CELL(0.511 ns) = 8.387 ns; Loc. = LC_X11_Y8_N0; Fanout = 12; COMB Node = 'song:inst\|WideNor0'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.804 ns" { song:inst|WideNor0~75 song:inst|WideNor0 } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.564 ns) + CELL(0.591 ns) 11.542 ns song:inst\|origin\[5\] 7 REG LC_X10_Y9_N2 2 " "Info: 7: + IC(2.564 ns) + CELL(0.591 ns) = 11.542 ns; Loc. = LC_X10_Y9_N2; Fanout = 2; REG Node = 'song:inst\|origin\[5\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.155 ns" { song:inst|WideNor0 song:inst|origin[5] } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.064 ns ( 26.55 % ) " "Info: Total cell delay = 3.064 ns ( 26.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.478 ns ( 73.45 % ) " "Info: Total interconnect delay = 8.478 ns ( 73.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.542 ns" { song:inst|med[1] song:inst|Equal1~154 song:inst|Equal3~146 song:inst|Selector3~164 song:inst|WideNor0~75 song:inst|WideNor0 song:inst|origin[5] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "11.542 ns" { song:inst|med[1] {} song:inst|Equal1~154 {} song:inst|Equal3~146 {} song:inst|Selector3~164 {} song:inst|WideNor0~75 {} song:inst|WideNor0 {} song:inst|origin[5] {} } { 0.000ns 1.283ns 1.817ns 0.738ns 0.783ns 1.293ns 2.564ns } { 0.000ns 0.740ns 0.511ns 0.200ns 0.511ns 0.511ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.136 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.136 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 27; CLK Node = 'clk'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { { 152 48 216 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv4:inst1\|clock_int 2 REG LC_X12_Y3_N9 30 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N9; Fanout = 30; REG Node = 'clockdiv4:inst1\|clock_int'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv4:inst1|clock_int } "NODE_NAME" } } { "clockdiv4.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/clockdiv4.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.023 ns) + CELL(0.918 ns) 8.136 ns song:inst\|origin\[5\] 3 REG LC_X10_Y9_N2 2 " "Info: 3: + IC(3.023 ns) + CELL(0.918 ns) = 8.136 ns; Loc. = LC_X10_Y9_N2; Fanout = 2; REG Node = 'song:inst\|origin\[5\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.941 ns" { clockdiv4:inst1|clock_int song:inst|origin[5] } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.48 % ) " "Info: Total cell delay = 3.375 ns ( 41.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.761 ns ( 58.52 % ) " "Info: Total interconnect delay = 4.761 ns ( 58.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { clk clockdiv4:inst1|clock_int song:inst|origin[5] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { clk {} clk~combout {} clockdiv4:inst1|clock_int {} song:inst|origin[5] {} } { 0.000ns 0.000ns 1.738ns 3.023ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.136 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.136 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 27; CLK Node = 'clk'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/Block1.bdf" { { 152 48 216 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv4:inst1\|clock_int 2 REG LC_X12_Y3_N9 30 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N9; Fanout = 30; REG Node = 'clockdiv4:inst1\|clock_int'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv4:inst1|clock_int } "NODE_NAME" } } { "clockdiv4.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/clockdiv4.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.023 ns) + CELL(0.918 ns) 8.136 ns song:inst\|med\[1\] 3 REG LC_X13_Y8_N7 10 " "Info: 3: + IC(3.023 ns) + CELL(0.918 ns) = 8.136 ns; Loc. = LC_X13_Y8_N7; Fanout = 10; REG Node = 'song:inst\|med\[1\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.941 ns" { clockdiv4:inst1|clock_int song:inst|med[1] } "NODE_NAME" } } { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.48 % ) " "Info: Total cell delay = 3.375 ns ( 41.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.761 ns ( 58.52 % ) " "Info: Total interconnect delay = 4.761 ns ( 58.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { clk clockdiv4:inst1|clock_int song:inst|med[1] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { clk {} clk~combout {} clockdiv4:inst1|clock_int {} song:inst|med[1] {} } { 0.000ns 0.000ns 1.738ns 3.023ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { clk clockdiv4:inst1|clock_int song:inst|origin[5] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { clk {} clk~combout {} clockdiv4:inst1|clock_int {} song:inst|origin[5] {} } { 0.000ns 0.000ns 1.738ns 3.023ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { clk clockdiv4:inst1|clock_int song:inst|med[1] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { clk {} clk~combout {} clockdiv4:inst1|clock_int {} song:inst|med[1] {} } { 0.000ns 0.000ns 1.738ns 3.023ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 41 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "song.v" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Speaker/song.v" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.542 ns" { song:inst|med[1] song:inst|Equal1~154 song:inst|Equal3~146 song:inst|Selector3~164 song:inst|WideNor0~75 song:inst|WideNor0 song:inst|origin[5] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "11.542 ns" { song:inst|med[1] {} song:inst|Equal1~154 {} song:inst|Equal3~146 {} song:inst|Selector3~164 {} song:inst|WideNor0~75 {} song:inst|WideNor0 {} song:inst|origin[5] {} } { 0.000ns 1.283ns 1.817ns 0.738ns 0.783ns 1.293ns 2.564ns } { 0.000ns 0.740ns 0.511ns 0.200ns 0.511ns 0.511ns 0.591ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { clk clockdiv4:inst1|clock_int song:inst|origin[5] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { clk {} clk~combout {} clockdiv4:inst1|clock_int {} song:inst|origin[5] {} } { 0.000ns 0.000ns 1.738ns 3.023ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { clk clockdiv4:inst1|clock_int song:inst|med[1] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { clk {} clk~combout {} clockdiv4:inst1|clock_int {} song:inst|med[1] {} } { 0.000ns 0.000ns 1.738ns 3.023ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}