song.map.rpt

speaker code,for thinx cpld

+-------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                             ;
+---------------------------------------------+---------------------------+
; Resource                                    ; Usage                     ;
+---------------------------------------------+---------------------------+
; Total logic elements                        ; 176                       ;
;     -- Combinational with no register       ; 105                       ;
;     -- Register only                        ; 22                        ;
;     -- Combinational with a register        ; 49                        ;
;                                             ;                           ;
; Logic element usage by number of LUT inputs ;                           ;
;     -- 4 input functions                    ; 64                        ;
;     -- 3 input functions                    ; 32                        ;
;     -- 2 input functions                    ; 53                        ;
;     -- 1 input functions                    ; 5                         ;
;     -- 0 input functions                    ; 0                         ;
;                                             ;                           ;
; Logic elements by mode                      ;                           ;
;     -- normal mode                          ; 134                       ;
;     -- arithmetic mode                      ; 42                        ;
;     -- qfbk mode                            ; 0                         ;
;     -- register cascade mode                ; 0                         ;
;     -- synchronous clear/load mode          ; 18                        ;
;     -- asynchronous clear/load mode         ; 0                         ;
;                                             ;                           ;
; Total registers                             ; 71                        ;
; Total logic cells in carry chains           ; 45                        ;
; I/O pins                                    ; 2                         ;
; Maximum fan-out node                        ; clockdiv4:inst1|clock_int ;
; Maximum fan-out                             ; 30                        ;
; Total fan-out                               ; 600                       ;
; Average fan-out                             ; 3.37                      ;
+---------------------------------------------+---------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name     ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+--------------+
; |Block1                    ; 176 (0)     ; 71           ; 0           ; 0            ; 0       ; 0         ; 0         ; 2    ; 0            ; 105 (0)      ; 22 (0)            ; 49 (0)           ; 45 (0)          ; 0 (0)      ; |Block1                 ; work         ;
;    |clockdiv4:inst1|       ; 54 (54)     ; 24           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 30 (30)      ; 15 (15)           ; 9 (9)            ; 23 (23)         ; 0 (0)      ; |Block1|clockdiv4:inst1 ; work         ;
;    |clockdiv6:inst2|       ; 3 (3)       ; 3            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |Block1|clockdiv6:inst2 ; work         ;
;    |song:inst|             ; 119 (119)   ; 44           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 75 (75)      ; 7 (7)             ; 37 (37)          ; 22 (22)         ; 0 (0)      ; |Block1|song:inst       ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; song:inst|med[3]                      ; Stuck at GND due to stuck port data_in ;
; song:inst|low[3]                      ; Stuck at GND due to stuck port data_in ;
; song:inst|high[1..3]                  ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 5 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 71    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 18    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 7     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 256:1              ; 7 bits    ; 1190 LEs      ; 175 LEs              ; 1015 LEs               ; Yes        ; |Block1|song:inst|med[2]   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Thu Jun 26 11:38:35 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off block1 -c song
Info: Found 2 design units, including 1 entities, in source file clockdiv6.vhd
    Info: Found design unit 1: clockdiv6-behavioural
    Info: Found entity 1: clockdiv6
Info: Found 2 design units, including 1 entities, in source file clockdiv4.vhd
    Info: Found design unit 1: clockdiv4-behavioural
    Info: Found entity 1: clockdiv4
Info: Found 1 design units, including 1 entities, in source file song.v
    Info: Found entity 1: song
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Elaborating entity "Block1" for the top level hierarchy
Warning: Processing legacy GDF or BDF entity "Block1" with Max+Plus II bus and instance naming rules
Info: Elaborating entity "song" for hierarchy "song:inst"
Warning (10230): Verilog HDL assignment warning at song.v(16): truncated value with size 32 to match size of target (14)
Warning (10230): Verilog HDL assignment warning at song.v(44): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "clockdiv6" for hierarchy "clockdiv6:inst2"
Info: Elaborating entity "clockdiv4" for hierarchy "clockdiv4:inst1"
Warning (14130): Reduced register "song:inst|med[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "song:inst|low[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "song:inst|high[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "song:inst|high[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "song:inst|high[3]" with stuck data_in port to stuck value GND
Info: Implemented 178 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 176 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Allocated 161 megabytes of memory during processing
    Info: Processing ended: Thu Jun 26 11:38:39 2008
    Info: Elapsed time: 00:00:04