📄 converter.tan.rpt
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Classic Timing Analyzer report for converter
Thu Jun 26 11:40:13 2008
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 8.884 ns ; DB2[3] ; SEG2[4] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM1270GT144C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+----------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+--------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+--------+---------+
; N/A ; None ; 8.884 ns ; DB2[3] ; SEG2[4] ;
; N/A ; None ; 8.738 ns ; DB2[1] ; SEG2[4] ;
; N/A ; None ; 8.581 ns ; DB[3] ; SEG[1] ;
; N/A ; None ; 8.482 ns ; DB[0] ; SEG[1] ;
; N/A ; None ; 8.471 ns ; DB[3] ; SEG[5] ;
; N/A ; None ; 8.446 ns ; DB[3] ; SEG[6] ;
; N/A ; None ; 8.438 ns ; DB2[0] ; SEG2[4] ;
; N/A ; None ; 8.431 ns ; DB[3] ; SEG[0] ;
; N/A ; None ; 8.404 ns ; DB[3] ; SEG[3] ;
; N/A ; None ; 8.380 ns ; DB[0] ; SEG[5] ;
; N/A ; None ; 8.378 ns ; DB2[2] ; SEG2[4] ;
; N/A ; None ; 8.371 ns ; DB[1] ; SEG[1] ;
; N/A ; None ; 8.370 ns ; DB[0] ; SEG[0] ;
; N/A ; None ; 8.360 ns ; DB[0] ; SEG[6] ;
; N/A ; None ; 8.348 ns ; DB[0] ; SEG[3] ;
; N/A ; None ; 8.261 ns ; DB[1] ; SEG[5] ;
; N/A ; None ; 8.238 ns ; DB[1] ; SEG[6] ;
; N/A ; None ; 8.227 ns ; DB[1] ; SEG[0] ;
; N/A ; None ; 8.206 ns ; DB[1] ; SEG[3] ;
; N/A ; None ; 7.980 ns ; DB[2] ; SEG[1] ;
; N/A ; None ; 7.942 ns ; DB2[3] ; SEG2[5] ;
; N/A ; None ; 7.940 ns ; DB2[3] ; SEG2[1] ;
; N/A ; None ; 7.930 ns ; DB2[3] ; SEG2[6] ;
; N/A ; None ; 7.927 ns ; DB2[3] ; SEG2[2] ;
; N/A ; None ; 7.925 ns ; DB2[3] ; SEG2[3] ;
; N/A ; None ; 7.924 ns ; DB2[3] ; SEG2[0] ;
; N/A ; None ; 7.879 ns ; DB[2] ; SEG[5] ;
; N/A ; None ; 7.873 ns ; DB[2] ; SEG[0] ;
; N/A ; None ; 7.860 ns ; DB[2] ; SEG[6] ;
; N/A ; None ; 7.851 ns ; DB[2] ; SEG[3] ;
; N/A ; None ; 7.220 ns ; DB[1] ; SEG[2] ;
; N/A ; None ; 7.217 ns ; DB[1] ; SEG[4] ;
; N/A ; None ; 7.153 ns ; DB2[0] ; SEG2[2] ;
; N/A ; None ; 7.152 ns ; DB2[0] ; SEG2[3] ;
; N/A ; None ; 7.145 ns ; DB2[0] ; SEG2[0] ;
; N/A ; None ; 7.143 ns ; DB2[0] ; SEG2[5] ;
; N/A ; None ; 7.142 ns ; DB2[0] ; SEG2[1] ;
; N/A ; None ; 7.139 ns ; DB2[0] ; SEG2[6] ;
; N/A ; None ; 7.123 ns ; DB2[1] ; SEG2[2] ;
; N/A ; None ; 7.122 ns ; DB2[1] ; SEG2[3] ;
; N/A ; None ; 7.114 ns ; DB2[1] ; SEG2[0] ;
; N/A ; None ; 7.108 ns ; DB2[1] ; SEG2[1] ;
; N/A ; None ; 7.106 ns ; DB2[1] ; SEG2[6] ;
; N/A ; None ; 7.098 ns ; DB2[1] ; SEG2[5] ;
; N/A ; None ; 7.096 ns ; DB[3] ; SEG[2] ;
; N/A ; None ; 7.093 ns ; DB2[2] ; SEG2[2] ;
; N/A ; None ; 7.093 ns ; DB[3] ; SEG[4] ;
; N/A ; None ; 7.092 ns ; DB2[2] ; SEG2[3] ;
; N/A ; None ; 7.085 ns ; DB2[2] ; SEG2[0] ;
; N/A ; None ; 7.082 ns ; DB2[2] ; SEG2[5] ;
; N/A ; None ; 7.081 ns ; DB2[2] ; SEG2[1] ;
; N/A ; None ; 7.079 ns ; DB2[2] ; SEG2[6] ;
; N/A ; None ; 6.529 ns ; DB[2] ; SEG[2] ;
; N/A ; None ; 6.522 ns ; DB[2] ; SEG[4] ;
; N/A ; None ; 5.943 ns ; DB[0] ; SEG[2] ;
; N/A ; None ; 5.937 ns ; DB[0] ; SEG[4] ;
+-------+-------------------+-----------------+--------+---------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
Info: Processing started: Thu Jun 26 11:40:13 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off change -c converter
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "DB2[3]" to destination pin "SEG2[4]" is 8.884 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 7; PIN Node = 'DB2[3]'
Info: 2: + IC(3.024 ns) + CELL(0.511 ns) = 4.667 ns; Loc. = LC_X1_Y7_N1; Fanout = 1; COMB Node = 'SEG2~812'
Info: 3: + IC(1.895 ns) + CELL(2.322 ns) = 8.884 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'SEG2[4]'
Info: Total cell delay = 3.965 ns ( 44.63 % )
Info: Total interconnect delay = 4.919 ns ( 55.37 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 112 megabytes of memory during processing
Info: Processing ended: Thu Jun 26 11:40:14 2008
Info: Elapsed time: 00:00:01
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