converter.vhd

来自「Seven code code,for thinx cpld」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY  converter  IS	
	PORT(	DB	: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
			SEG : OUT	STD_LOGIC_VECTOR(6 DOWNTO 0);
			DB2	: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
			SEG2 : OUT	STD_LOGIC_VECTOR(6 DOWNTO 0));
END converter;
ARCHITECTURE a OF converter IS	
BEGIN
	SEG<=   "1111110" WHEN DB="0000" ELSE
			"0110000" WHEN DB="0001" ELSE
			"1101101" WHEN DB="0010" ELSE
			"1111001" WHEN DB="0011" ELSE
			"0110011" WHEN DB="0100" ELSE
			"1011011" WHEN DB="0101" ELSE
			"1011111" WHEN DB="0110" ELSE
			"1110000" WHEN DB="0111" ELSE
			"1111111" WHEN DB="1000" ELSE
			"1111011" WHEN DB="1001" ELSE
			"0000000" ;
	SEG2<=  "1111110" WHEN DB2="0000" ELSE
			"0110000" WHEN DB2="0001" ELSE
			"1101101" WHEN DB2="0010" ELSE
			"1111001" WHEN DB2="0011" ELSE
			"0110011" WHEN DB2="0100" ELSE
			"1011011" WHEN DB2="0101" ELSE
			"1011111" WHEN DB2="0110" ELSE
			"1110000" WHEN DB2="0111" ELSE
			"1111111" WHEN DB2="1000" ELSE
			"1111011" WHEN DB2="1001" ELSE
			"0000000" ;
END a;