📄 mfrc50~1.lis
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0120 ; *atq = 0;
0120 2224 clr R2
0122 FB01 movw R30,R22
0124 2082 std z+0,R2
0126 .dbline 75
0126 ; }
0126 18C0 xjmp L20
0128 L19:
0128 .dbline 77
0128 ; else
0128 ; {
0128 .dbline 78
0128 ; if (MInfo.nBitsReceived != 16) // 2 bytes expected
0128 80910801 lds R24,_MInfo+6
012C 90910901 lds R25,_MInfo+6+1
0130 8031 cpi R24,16
0132 E0E0 ldi R30,0
0134 9E07 cpc R25,R30
0136 19F0 breq L21
0138 .dbline 79
0138 ; {
0138 .dbline 80
0138 ; status = MI_BITCOUNTERR;
0138 45EF ldi R20,-11
013A 5FEF ldi R21,-1
013C .dbline 81
013C ; }
013C 0DC0 xjmp L22
013E L21:
013E .dbline 83
013E ; else
013E ; {
013E .dbline 84
013E ; status = MI_OK;
013E 4427 clr R20
0140 5527 clr R21
0142 .dbline 85
0142 ; memcpy(atq,MRcvBuffer,2);
0142 82E0 ldi R24,2
0144 90E0 ldi R25,0
0146 9983 std y+1,R25
0148 8883 std y+0,R24
014A 20910C01 lds R18,_MRcvBuffer
014E 30910D01 lds R19,_MRcvBuffer+1
0152 8B01 movw R16,R22
0154 0E940000 xcall _memcpy
0158 .dbline 86
0158 ; }
0158 L22:
0158 .dbline 87
0158 ; }
0158 L20:
0158 .dbline 88
0158 ; return status;
0158 042F mov R16,R20
015A .dbline -2
015A L10:
015A 2496 adiw R28,4
015C 0E940000 xcall pop_gset3
0160 .dbline 0 ; func end
0160 0895 ret
0162 .dbsym r status 20 I
0162 .dbsym r atq 22 pc
0162 .dbsym r req_code 10 c
0162 .dbend
0162 .dbfunc e Mf500PiccAnticoll _Mf500PiccAnticoll fc
0162 ; snr -> R22,R23
0162 ; bcnt -> R20
.even
0162 _Mf500PiccAnticoll::
0162 0E940000 xcall push_gset2
0166 B901 movw R22,R18
0168 402F mov R20,R16
016A 2297 sbiw R28,2
016C .dbline -1
016C .dbline 96
016C ; }
016C ; ///////////////////////////////////////////////////////////////////////
016C ; // M I F A R E A N T I C O L L I S I O N
016C ; // for standard select
016C ; ///////////////////////////////////////////////////////////////////////
016C ; char Mf500PiccAnticoll (unsigned char bcnt,
016C ; unsigned char *snr)
016C ; {
016C .dbline 97
016C ; return Mf500PiccCascAnticoll(0x93,bcnt,snr); // first cascade level
016C 7983 std y+1,R23
016E 6883 std y+0,R22
0170 242F mov R18,R20
0172 03E9 ldi R16,147
0174 04D0 xcall _Mf500PiccCascAnticoll
0176 .dbline -2
0176 L24:
0176 2296 adiw R28,2
0178 0E940000 xcall pop_gset2
017C .dbline 0 ; func end
017C 0895 ret
017E .dbsym r snr 22 pc
017E .dbsym r bcnt 20 c
017E .dbend
017E .dbfunc e Mf500PiccCascAnticoll _Mf500PiccCascAnticoll fc
017E ; snr_check -> R14
017E ; snr_crc -> R20
017E ; complete -> R10
017E ; byteOffset -> R22
017E ; status -> y+10
017E ; nbits -> y+9
017E ; dummyShift2 -> R14
017E ; dummyShift1 -> R20
017E ; snr_in -> y+4
017E ; nbytes -> y+8
017E ; i -> R12
017E ; snr -> y+26
017E ; bcnt -> y+24
017E ; select_code -> y+22
.even
017E _Mf500PiccCascAnticoll::
017E 0E940000 xcall push_arg4
0182 0E940000 xcall push_gset5
0186 2C97 sbiw R28,12
0188 .dbline -1
0188 .dbline 100
0188 ; }
0188 ; char Mf500PiccCascAnticoll(unsigned char select_code,unsigned char bcnt,unsigned char *snr)
0188 ; {
0188 .dbline 101
0188 ; int status = MI_OK;
0188 0024 clr R0
018A 1124 clr R1
018C 1B86 std y+11,R1
018E 0A86 std y+10,R0
0190 .dbline 103
0190 ; char snr_in[4]; // copy of the input parameter snr
0190 ; char nbytes = 0; // how many bytes received
0190 0886 std y+8,R0
0192 .dbline 104
0192 ; char nbits = 0; // how many bits received
0192 0986 std y+9,R0
0194 .dbline 105
0194 ; char complete = 0; // complete snr recived
0194 AA24 clr R10
0196 .dbline 106
0196 ; char i = 0;
0196 CC24 clr R12
0198 .dbline 107
0198 ; char byteOffset = 0;
0198 6627 clr R22
019A .dbline 113
019A ; unsigned char snr_crc; // check byte calculation
019A ; unsigned char snr_check;
019A ; unsigned char dummyShift1; // dummy byte for snr shift
019A ; unsigned char dummyShift2; // dummy byte for snr shift
019A ; //************* Initialisierung ******************************
019A ; if ((status = Mf500PcdSetDefaultAttrib()) == MI_OK)
019A 30D2 xcall _Mf500PcdSetDefaultAttrib
019C 202E mov R2,R16
019E 3324 clr R3
01A0 3B86 std y+11,R3
01A2 2A86 std y+10,R2
01A4 0023 tst R16
01A6 09F0 breq X5
01A8 66C1 xjmp L26
01AA X5:
01AA .dbline 114
01AA ; {
01AA .dbline 115
01AA ; PcdSetTmo(106);
01AA 0AE6 ldi R16,106
01AC 10E0 ldi R17,0
01AE F2D5 xcall _PcdSetTmo
01B0 .dbline 116
01B0 ; memcpy(snr_in,snr,4);
01B0 84E0 ldi R24,4
01B2 90E0 ldi R25,0
01B4 9983 std y+1,R25
01B6 8883 std y+0,R24
01B8 2A8D ldd R18,y+26
01BA 3B8D ldd R19,y+27
01BC 8E01 movw R16,R28
01BE 0C5F subi R16,252 ; offset = 4
01C0 1F4F sbci R17,255
01C2 0E940000 xcall _memcpy
01C6 .dbline 117
01C6 ; WriteRC(RegDecoderControl,0x28); // ZeroAfterColl aktivieren
01C6 28E2 ldi R18,40
01C8 0AE1 ldi R16,26
01CA 0E94C509 xcall _WriteRC
01CE .dbline 118
01CE ; ClearBitMask(RegControl,0x08); // disable crypto 1 unit
01CE 28E0 ldi R18,8
01D0 09E0 ldi R16,9
01D2 28D6 xcall _ClearBitMask
01D4 .dbline 120
01D4 ; //************** Anticollision Loop ***************************
01D4 ; complete=0;
01D4 47C1 xjmp L29
01D6 L28:
01D6 .dbline 122
01D6 ; while (!complete && (status == MI_OK) )
01D6 ; {
01D6 .dbline 123
01D6 ; ResetInfo(MInfo);
01D6 2224 clr R2
01D8 20920201 sts _MInfo,R2
01DC .dbline 123
01DC 3324 clr R3
01DE 30920401 sts _MInfo+1+1,R3
01E2 20920301 sts _MInfo+1,R2
01E6 .dbline 123
01E6 20920501 sts _MInfo+3,R2
01EA .dbline 123
01EA 20920601 sts _MInfo+4,R2
01EE .dbline 123
01EE 20920701 sts _MInfo+5,R2
01F2 .dbline 123
01F2 30920901 sts _MInfo+6+1,R3
01F6 20920801 sts _MInfo+6,R2
01FA .dbline 123
01FA 20920A01 sts _MInfo+8,R2
01FE .dbline 123
01FE 20920B01 sts _MInfo+9,R2
0202 .dbline 123
0202 .dbline 124
0202 ; WriteRC(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
0202 23E0 ldi R18,3
0204 02E2 ldi R16,34
0206 0E94C509 xcall _WriteRC
020A .dbline 125
020A ; nbits = bcnt % 8; // remaining number of bits
020A 18E0 ldi R17,8
020C 088D ldd R16,y+24
020E 0E940000 xcall mod8u
0212 0987 std y+9,R16
0214 .dbline 126
0214 ; if (nbits)
0214 002E mov R0,R16
0216 0023 tst R16
0218 C1F0 breq L38
021A .dbline 127
021A ; {
021A .dbline 128
021A ; WriteRC(RegBitFraming,nbits << 4 | nbits); // TxLastBits/RxAlign auf nb_bi
021A 202D mov R18,R0
021C 2F70 andi R18,#0x0F
021E 2295 swap R18
0220 202B or R18,R16
0222 0FE0 ldi R16,15
0224 0E94C509 xcall _WriteRC
0228 .dbline 129
0228 ; nbytes = bcnt / 8 + 1;
0228 888D ldd R24,y+24
022A 8695 lsr R24
022C 8695 lsr R24
022E 8695 lsr R24
0230 8F5F subi R24,255 ; addi 1
0232 8887 std y+8,R24
0234 .dbline 130
0234 ; if (nbits == 7 )
0234 8985 ldd R24,y+9
0236 8730 cpi R24,7
0238 69F4 brne L39
023A .dbline 131
023A ; {
023A .dbline 132
023A ; MInfo.cmd = PICC_ANTICOLL1; // pass command flag to ISR
023A 83E9 ldi R24,147
023C 80930201 sts _MInfo,R24
0240 .dbline 133
0240 ; WriteRC(RegBitFraming,nbits); // reset RxAlign to zero
0240 2985 ldd R18,y+9
0242 0FE0 ldi R16,15
0244 0E94C509 xcall _WriteRC
0248 .dbline 134
0248 ; }
0248 .dbline 135
0248 ; }
0248 05C0 xjmp L39
024A L38:
024A .dbline 137
024A ; else
024A ; {
024A .dbline 138
024A ; nbytes = bcnt / 8;
024A 288C ldd R2,y+24
024C 2694 lsr R2
024E 2694 lsr R2
0250 2694 lsr R2
0252 2886 std y+8,R2
0254 .dbline 139
0254 ; }
0254 L39:
0254 .dbline 140
0254 ; MSndBuffer[0] = select_code;
0254 E0910E01 lds R30,_MSndBuffer
0258 F0910F01 lds R31,_MSndBuffer+1
025C 0E88 ldd R0,y+22
025E 0082 std z+0,R0
0260 .dbline 141
0260 ; MSndBuffer[1] = 0x20 + ((bcnt/8) << 4) + nbits; //number of bytes send
0260 888D ldd R24,y+24
0262 8695 lsr R24
0264 8695 lsr R24
0266 8695 lsr R24
0268 8F70 andi R24,#0x0F
026A 8295 swap R24
026C 805E subi R24,224 ; addi 32
026E 0984 ldd R0,y+9
0270 800D add R24,R0
0272 8183 std z+1,R24
0274 .dbline 142
0274 ; for (i = 0; i < nbytes; i++) // Sende Buffer beschreiben
0274 CC24 clr R12
0276 11C0 xjmp L45
0278 L42:
0278 .dbline 143
0278 .dbline 144
0278 CE01 movw R24,R28
027A 0496 adiw R24,4
027C EC2D mov R30,R12
027E FF27 clr R31
0280 E80F add R30,R24
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