📄 mfrc500uc.lis
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0126 .dbline 74
0126 ; *atq = 0;
0126 2224 clr R2
0128 FB01 movw R30,R22
012A 2082 std z+0,R2
012C .dbline 75
012C ; }
012C 18C0 xjmp L20
012E L19:
012E .dbline 77
012E ; else
012E ; {
012E .dbline 78
012E ; if (MInfo.nBitsReceived != 16) // 2 bytes expected
012E 80910801 lds R24,_MInfo+6
0132 90910901 lds R25,_MInfo+6+1
0136 8031 cpi R24,16
0138 E0E0 ldi R30,0
013A 9E07 cpc R25,R30
013C 19F0 breq L21
013E .dbline 79
013E ; {
013E .dbline 80
013E ; status = MI_BITCOUNTERR;
013E 45EF ldi R20,-11
0140 5FEF ldi R21,-1
0142 .dbline 81
0142 ; }
0142 0DC0 xjmp L22
0144 L21:
0144 .dbline 83
0144 ; else
0144 ; {
0144 .dbline 84
0144 ; status = MI_OK;
0144 4427 clr R20
0146 5527 clr R21
0148 .dbline 85
0148 ; memcpy(atq,MRcvBuffer,2);
0148 82E0 ldi R24,2
014A 90E0 ldi R25,0
014C 9983 std y+1,R25
014E 8883 std y+0,R24
0150 20910C01 lds R18,_MRcvBuffer
0154 30910D01 lds R19,_MRcvBuffer+1
0158 8B01 movw R16,R22
015A 0E940000 xcall _memcpy
015E .dbline 86
015E ; }
015E L22:
015E .dbline 87
015E ; }
015E L20:
015E .dbline 88
015E ; return status;
015E 042F mov R16,R20
0160 .dbline -2
0160 L10:
0160 2496 adiw R28,4
0162 0E940000 xcall pop_gset3
0166 .dbline 0 ; func end
0166 0895 ret
0168 .dbsym r status 20 I
0168 .dbsym r atq 22 pc
0168 .dbsym r req_code 10 c
0168 .dbend
0168 .dbfunc e Mf500PiccAnticoll _Mf500PiccAnticoll fc
0168 ; snr -> R22,R23
0168 ; bcnt -> R20
.even
0168 _Mf500PiccAnticoll::
0168 0E940000 xcall push_gset2
016C B901 movw R22,R18
016E 402F mov R20,R16
0170 2297 sbiw R28,2
0172 .dbline -1
0172 .dbline 96
0172 ; }
0172 ; ///////////////////////////////////////////////////////////////////////
0172 ; // M I F A R E A N T I C O L L I S I O N
0172 ; // for standard select
0172 ; ///////////////////////////////////////////////////////////////////////
0172 ; char Mf500PiccAnticoll (unsigned char bcnt,
0172 ; unsigned char *snr)
0172 ; {
0172 .dbline 97
0172 ; return Mf500PiccCascAnticoll(0x93,bcnt,snr); // first cascade level
0172 7983 std y+1,R23
0174 6883 std y+0,R22
0176 242F mov R18,R20
0178 03E9 ldi R16,147
017A 04D0 xcall _Mf500PiccCascAnticoll
017C .dbline -2
017C L24:
017C 2296 adiw R28,2
017E 0E940000 xcall pop_gset2
0182 .dbline 0 ; func end
0182 0895 ret
0184 .dbsym r snr 22 pc
0184 .dbsym r bcnt 20 c
0184 .dbend
0184 .dbfunc e Mf500PiccCascAnticoll _Mf500PiccCascAnticoll fc
0184 ; snr_check -> R14
0184 ; snr_crc -> R20
0184 ; complete -> R10
0184 ; byteOffset -> R22
0184 ; status -> y+10
0184 ; nbits -> y+9
0184 ; dummyShift2 -> R14
0184 ; dummyShift1 -> R20
0184 ; snr_in -> y+4
0184 ; nbytes -> y+8
0184 ; i -> R12
0184 ; snr -> y+26
0184 ; bcnt -> y+24
0184 ; select_code -> y+22
.even
0184 _Mf500PiccCascAnticoll::
0184 0E940000 xcall push_arg4
0188 0E940000 xcall push_gset5
018C 2C97 sbiw R28,12
018E .dbline -1
018E .dbline 100
018E ; }
018E ; char Mf500PiccCascAnticoll(unsigned char select_code,unsigned char bcnt,unsigned char *snr)
018E ; {
018E .dbline 101
018E ; int status = MI_OK;
018E 0024 clr R0
0190 1124 clr R1
0192 1B86 std y+11,R1
0194 0A86 std y+10,R0
0196 .dbline 103
0196 ; char snr_in[4]; // copy of the input parameter snr
0196 ; char nbytes = 0; // how many bytes received
0196 0886 std y+8,R0
0198 .dbline 104
0198 ; char nbits = 0; // how many bits received
0198 0986 std y+9,R0
019A .dbline 105
019A ; char complete = 0; // complete snr recived
019A AA24 clr R10
019C .dbline 106
019C ; char i = 0;
019C CC24 clr R12
019E .dbline 107
019E ; char byteOffset = 0;
019E 6627 clr R22
01A0 .dbline 113
01A0 ; unsigned char snr_crc; // check byte calculation
01A0 ; unsigned char snr_check;
01A0 ; unsigned char dummyShift1; // dummy byte for snr shift
01A0 ; unsigned char dummyShift2; // dummy byte for snr shift
01A0 ; //************* Initialisierung ******************************
01A0 ; if ((status = Mf500PcdSetDefaultAttrib()) == MI_OK)
01A0 38D2 xcall _Mf500PcdSetDefaultAttrib
01A2 202E mov R2,R16
01A4 3324 clr R3
01A6 3B86 std y+11,R3
01A8 2A86 std y+10,R2
01AA 0023 tst R16
01AC 09F0 breq X5
01AE 6AC1 xjmp L26
01B0 X5:
01B0 .dbline 114
01B0 ; {
01B0 .dbline 115
01B0 ; PcdSetTmo(106);
01B0 0AE6 ldi R16,106
01B2 10E0 ldi R17,0
01B4 14D6 xcall _PcdSetTmo
01B6 .dbline 116
01B6 ; memcpy(snr_in,snr,4);
01B6 84E0 ldi R24,4
01B8 90E0 ldi R25,0
01BA 9983 std y+1,R25
01BC 8883 std y+0,R24
01BE 2A8D ldd R18,y+26
01C0 3B8D ldd R19,y+27
01C2 8E01 movw R16,R28
01C4 0C5F subi R16,252 ; offset = 4
01C6 1F4F sbci R17,255
01C8 0E940000 xcall _memcpy
01CC .dbline 117
01CC ; WriteRC(RegDecoderControl,0x28); // ZeroAfterColl aktivieren
01CC 28E2 ldi R18,40
01CE 0AE1 ldi R16,26
01D0 0E94EB09 xcall _WriteRC
01D4 .dbline 118
01D4 ; ClearBitMask(RegControl,0x08); // disable crypto 1 unit
01D4 28E0 ldi R18,8
01D6 09E0 ldi R16,9
01D8 4AD6 xcall _ClearBitMask
01DA .dbline 120
01DA ; //************** Anticollision Loop ***************************
01DA ; complete=0;
01DA 4BC1 xjmp L29
01DC L28:
01DC .dbline 122
01DC ; while (!complete && (status == MI_OK) )
01DC ; {
01DC .dbline 123
01DC ; ResetInfo(MInfo);
01DC 2224 clr R2
01DE 20920201 sts _MInfo,R2
01E2 .dbline 123
01E2 3324 clr R3
01E4 30920401 sts _MInfo+1+1,R3
01E8 20920301 sts _MInfo+1,R2
01EC .dbline 123
01EC 20920501 sts _MInfo+3,R2
01F0 .dbline 123
01F0 20920601 sts _MInfo+4,R2
01F4 .dbline 123
01F4 20920701 sts _MInfo+5,R2
01F8 .dbline 123
01F8 30920901 sts _MInfo+6+1,R3
01FC 20920801 sts _MInfo+6,R2
0200 .dbline 123
0200 20920A01 sts _MInfo+8,R2
0204 .dbline 123
0204 20920B01 sts _MInfo+9,R2
0208 .dbline 123
0208 .dbline 124
0208 ; WriteRC(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
0208 23E0 ldi R18,3
020A 02E2 ldi R16,34
020C 0E94EB09 xcall _WriteRC
0210 .dbline 125
0210 ; nbits = bcnt % 8; // remaining number of bits
0210 18E0 ldi R17,8
0212 088D ldd R16,y+24
0214 0E940000 xcall mod8u
0218 0987 std y+9,R16
021A .dbline 126
021A ; if (nbits)
021A 002E mov R0,R16
021C 0023 tst R16
021E C1F0 breq L38
0220 .dbline 127
0220 ; {
0220 .dbline 128
0220 ; WriteRC(RegBitFraming,nbits << 4 | nbits); // TxLastBits/RxAlign auf nb_bi
0220 202D mov R18,R0
0222 2F70 andi R18,#0x0F
0224 2295 swap R18
0226 202B or R18,R16
0228 0FE0 ldi R16,15
022A 0E94EB09 xcall _WriteRC
022E .dbline 129
022E ; nbytes = bcnt / 8 + 1;
022E 888D ldd R24,y+24
0230 8695 lsr R24
0232 8695 lsr R24
0234 8695 lsr R24
0236 8F5F subi R24,255 ; addi 1
0238 8887 std y+8,R24
023A .dbline 130
023A ; if (nbits == 7 )
023A 8985 ldd R24,y+9
023C 8730 cpi R24,7
023E 69F4 brne L39
0240 .dbline 131
0240 ; {
0240 .dbline 132
0240 ; MInfo.cmd = PICC_ANTICOLL1; // pass command flag to ISR
0240 83E9 ldi R24,147
0242 80930201 sts _MInfo,R24
0246 .dbline 133
0246 ; WriteRC(RegBitFraming,nbits); // reset RxAlign to zero
0246 2985 ldd R18,y+9
0248 0FE0 ldi R16,15
024A 0E94EB09 xcall _WriteRC
024E .dbline 134
024E ; }
024E .dbline 135
024E ; }
024E 05C0 xjmp L39
0250 L38:
0250 .dbline 137
0250 ; else
0250 ; {
0250 .dbline 138
0250 ; nbytes = bcnt / 8;
0250 288C ldd R2,y+24
0252 2694 lsr R2
0254 2694 lsr R2
0256 2694 lsr R2
0258 2886 std y+8,R2
025A .dbline 139
025A ; }
025A L39:
025A .dbline 140
025A ; MSndBuffer[0] = select_code;
025A E0910E01 lds R30,_MSndBuffer
025E F0910F01 lds R31,_MSndBuffer+1
0262 0E88 ldd R0,y+22
0264 0082 std z+0,R0
0266 .dbline 141
0266 ; MSndBuffer[1] = 0x20 + ((bcnt/8) << 4) + nbits; //number of bytes send
0266 888D ldd R24,y+24
0268 8695 lsr R24
026A 8695 lsr R24
026C 8695 lsr R24
026E 8F70 andi R24,#0x0F
0270 8295 swap R24
0272 805E subi R24,224 ; addi 32
0274 0984 ldd R0,y+9
0276 800D add R24,R0
0278 E0910E01 lds R30,_MSndBuffer
027C F0910F01 lds R31,_MSndBuffer+1
0280 8183 std z+1,R24
0282 .dbline 142
0282 ; for (i = 0; i < nbytes; i++) // Sende Buffer beschreiben
0282 CC24 clr R12
0284 11C0 xjmp L45
0286 L42:
0286 .dbline 143
0286 .dbline 144
0286 CE01 movw R24,R28
0288 0496 adiw R24,4
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