mfrc500.h

该程序是医院用的CPCR记录仪的终端控制程序

#define ResetInfo(info)    \
            info.cmd            = 0; \
            info.status         = MI_OK;\
			info.nBytesSent     = 0; \
            info.nBytesToSend   = 0; \
            info.nBytesReceived = 0; \
            info.nBitsReceived  = 0; \
			info.irqSource      = 0; \
			info.collPos        = 0; 
typedef struct 
   			{
            unsigned char  cmd;           //!< command code 
            int            status;        //!< communication status
            unsigned char  nBytesSent;    //!< how many bytes already sent
            unsigned char  nBytesToSend;  //!< how many bytes to send
            unsigned char  nBytesReceived;//!< how many bytes received
            unsigned short nBitsReceived; //!< how many bits received
            unsigned char  irqSource;     //!< which interrupts have occured
            unsigned char  collPos;       /*!< at which position occured a
                                          collision*/
         } MfCmdInfo;
 
#define GetRegPage(addr) (0x80 | (addr>>3))
#define PICC_REQIDL        0x26         //!< request idle
#define PICC_REQALL        0x52         //!< request all
#define PICC_ANTICOLL1     0x93         //!< anticollision level 1 106 kBaud
#define PICC_ANTICOLL2     0x95         //!< anticollision level 2
#define PICC_ANTICOLL3     0x97         //!< anticollision level 3
#define PICC_AUTHENT1A     0x60         //!< authentication using key A
#define PICC_AUTHENT1B     0x61         //!< authentication using key B
#define PICC_READ          0x30         //!< read block
#define PICC_WRITE         0xA0         //!< write block
#define PICC_DECREMENT     0xC0         //!< decrement value
#define PICC_INCREMENT     0xC1         //!< increment value
#define PICC_RESTORE       0xC2         //!< restore command code
#define PICC_TRANSFER      0xB0         //!< transfer command code
#define PICC_HALT          0x50         //!< halt


#define READER_ERR_BASE_START           0
#define MI_OK                           0
#define MI_CHK_OK                       0
#define MI_CRC_ZERO                     0

#define MI_CRC_NOTZERO                  1

#define MI_NOTAGERR                     (-1)
#define MI_CHK_FAILED                   (-1)
#define MI_CRCERR                       (-2)
#define MI_CHK_COMPERR                  (-2)
#define MI_EMPTY                        (-3)
#define MI_AUTHERR                      (-4)
#define MI_PARITYERR                    (-5)
#define MI_CODEERR                      (-6)

#define MI_SERNRERR                     (-8)
#define MI_KEYERR                       (-9)
#define MI_NOTAUTHERR                   (-10)
#define MI_BITCOUNTERR                  (-11)
#define MI_BYTECOUNTERR                 (-12)
#define MI_IDLE                         (-13)
#define MI_TRANSERR                     (-14)
#define MI_WRITEERR                     (-15)
#define MI_INCRERR                      (-16)
#define MI_DECRERR                      (-17)
#define MI_READERR                      (-18)
#define MI_OVFLERR                      (-19)
#define MI_POLLING                      (-20)
#define MI_FRAMINGERR                   (-21)
#define MI_ACCESSERR                    (-22)
#define MI_UNKNOWN_COMMAND              (-23)
#define MI_COLLERR                      (-24)
#define MI_RESETERR                     (-25)
#define MI_INITERR                      (-25)
#define MI_INTERFACEERR                 (-26)
#define MI_ACCESSTIMEOUT                (-27)
#define MI_NOBITWISEANTICOLL            (-28)
#define MI_QUIT                         (-30)

#define MI_RECBUF_OVERFLOW              (-50) 
#define MI_SENDBYTENR                   (-51)
	
#define MI_SENDBUF_OVERFLOW             (-53)
#define MI_BAUDRATE_NOT_SUPPORTED       (-54)
#define MI_SAME_BAUDRATE_REQUIRED       (-55)

#define MI_WRONG_PARAMETER_VALUE        (-60)

#define MI_BREAK                        (-99)
#define MI_NY_IMPLEMENTED               (-100)
#define MI_NO_MFRC                      (-101)
#define MI_MFRC_NOTAUTH                 (-102)
#define MI_WRONG_DES_MODE               (-103)
#define MI_HOST_AUTH_FAILED             (-104)

#define MI_WRONG_LOAD_MODE              (-106)
#define MI_WRONG_DESKEY                 (-107)
#define MI_MKLOAD_FAILED                (-108)
#define MI_FIFOERR                      (-109)
#define MI_WRONG_ADDR                   (-110)
#define MI_DESKEYLOAD_FAILED            (-111)

#define MI_WRONG_SEL_CNT                (-114)

#define MI_WRONG_TEST_MODE              (-117)
#define MI_TEST_FAILED                  (-118)
#define MI_TOC_ERROR                    (-119)
#define MI_COMM_ABORT                   (-120)
#define MI_INVALID_BASE                 (-121)
#define MI_MFRC_RESET                   (-122)
#define MI_WRONG_VALUE                  (-123)
#define MI_VALERR                       (-124)
 
#define     RegPage               0x00   //!< Page Select Register
#define     RegCommand            0x01   //!< Command Register
#define     RegFIFOData           0x02   //!< FiFo Register
#define     RegPrimaryStatus      0x03   //!< Modem State/IRQ/ERR/LoHiAlert Reg
#define     RegFIFOLength         0x04   //!< Buffer length Register
#define     RegSecondaryStatus    0x05   //!< diverse status flags
#define     RegInterruptEn        0x06   //!< IRQ enable Register
#define     RegInterruptRq        0x07   //!< IRQ bits Register
// PAGE 1      Control and Status
#define     RegControl            0x09   //!< processor control
#define     RegErrorFlag          0x0A   /*!< error flags showing the error 
                                         status of the last command executed */
#define     RegCollPos            0x0B   /*!< bit position of the first bit 
                                         collision detected on the 
                                         RF-interface */
#define     RegTimerValue         0x0C   //!< preload value of the timer
#define     RegCRCResultLSB       0x0D   //!< LSB of the CRC Coprocessor register
#define     RegCRCResultMSB       0x0E   //!< MSB of the CRC Coprocessor register
#define     RegBitFraming         0x0F   //!< Adjustments for bit oriented frames
// PAGE 2      Transmitter and Coder Control
#define     RegTxControl          0x11   //!< controls the logical behaviour of 
                                         //!< the antenna driver pins TX1 and TX2
#define     RegCwConductance      0x12   /*!< selects the conductance of the 
                                         antenna driver pins TX1 and TX2 */
#define     RFU13                 0x13   //!< RFU
#define     RegCoderControl       0x14   //!< selects coder rate
#define     RegModWidth           0x15   /*!< selects the width of the 
                                         modulation pulse */
#define     RFU16                 0x16   //!< RFU
#define     RFU17                 0x17   //!< RFU
// PAGE 3      Receiver and Decoder Control
#define     RegRxControl1         0x19   //!< controls receiver behaviour
#define     RegDecoderControl     0x1A   //!< controls decoder behaviour
#define     RegBitPhase           0x1B   /*!< selets the bit phase between 
                                         transmitter and receiver clock */
#define     RegRxThreshold        0x1C   /*!< selects thresholds for the bit 
                                         decoder */
#define     RFU1D                 0x1D   //!< RFU
#define     RegRxControl2         0x1E   /*!< controls decoder behaviour and 
                                         defines the input source for the 
                                         receiver */
#define     RegClockQControl      0x1F   /*!< controls clock generation for the 
                                         90