zbtsram.c

dsp常见的扩展外设的框架程序和测试程序

/*****************************************************************************
	FILENAME:	SDRAM.C
	DESIGNER:	戴展波
	DATE：		2004/09/25
******************************************************************************/

#include <stdio.h>
#include <csl.h>
#include <csl_irq.h>
#include <csl_chip.h>
#include <csl_emifa.h>
#include <csl_emifb.h>

static EMIFA_Config MyEmifaConfig = 
{
	EMIFA_GBLCTL_RMK
	(
		EMIFA_GBLCTL_EK2RATE_FULLCLK,	//1 X EMIF input clock
		EMIFA_GBLCTL_EK2HZ_CLK,		//eclkout2 continue output during hold
		EMIFA_GBLCTL_EK2EN_ENABLE,	//eclkout2 enable output
		EMIFA_GBLCTL_BRMODE_MRSTATUS,	//bus request is memory access or refresh pending/in progress
		EMIFA_GBLCTL_NOHOLD_DISABLE,
		EMIFA_GBLCTL_EK1HZ_CLK,		//eclkout1 continue output during hold
		EMIFA_GBLCTL_EK1EN_ENABLE,	//eclkout1 enable output
		EMIFA_GBLCTL_CLK4EN_ENABLE,	//clkout4 output enable
		EMIFA_GBLCTL_CLK6EN_ENABLE	//clkout6 output enable
	),
	0xffffffd3,
	0xffffffe3,		//64bit zbtsram
//	0xffffff43,		//32bit zbtsram
//	0xffffffb3,		//16bit zbtsram
//	0xffffffa3,		//8bit zbtsram
	0x22a28a22,
	0x22a28a22,
	EMIFA_SDCTL_DEFAULT,
	EMIFA_SDTIM_DEFAULT,
	EMIFA_SDEXT_DEFAULT,
	0x00000002,
	EMIFA_CESEC_RMK
	(
		EMIFA_CESEC_SNCCLK_ECLKOUT1,
		EMIFA_CESEC_RENEN_ADS,
		EMIFA_CESEC_CEEXT_INACTIVE,
		EMIFA_CESEC_SYNCWL_2CYCLE,
		EMIFA_CESEC_SYNCRL_2CYCLE
	),
	0x00000002,
	0x00000002
};

static EMIFB_Config MyEmifbConfig = 
{
	EMIFB_GBLCTL_RMK
	(
		EMIFB_GBLCTL_EK2RATE_FULLCLK,	//1 X EMIF input clock
		EMIFB_GBLCTL_EK2HZ_CLK,		//eclkout2 continue output during hold
		EMIFB_GBLCTL_EK2EN_ENABLE,	//eclkout2 enable output
		EMIFB_GBLCTL_BRMODE_MRSTATUS,	//bus request is memory access or refresh pending/in progress
		EMIFB_GBLCTL_NOHOLD_ENABLE,
		EMIFB_GBLCTL_EK1HZ_CLK,		//eclkout1 continue output during hold
		EMIFB_GBLCTL_EK1EN_ENABLE	//eclkout1 enable output
	),
	0x1120c301,
	0x22a28a22,
	0x22a28a22,
	0x22a28a22,
	EMIFB_SDCTL_DEFAULT,
	EMIFB_SDTIM_DEFAULT,
	EMIFB_SDEXT_DEFAULT,
	0x00000002,
	0x00000002,
	0x00000002,
	0x00000002
};

volatile unsigned char* ZBTSRAM_CE3 = (volatile unsigned char *) 0x60000020;

#pragma DATA_SECTION(zbtsram_data,".off_ram");
unsigned int zbtsram_data[0x10000];

extern far void vectors();

void main()
{
	int i;
	Uint32 good_flag;
	good_flag = 0;
	//初始化CSL
	CSL_init();
	//配置EMIFB
	EMIFB_config(&MyEmifbConfig);
	//打开ZBTSRAM
	*ZBTSRAM_CE3 = 0;
	//配置EMIFA
	EMIFA_config(&MyEmifaConfig);
	//设置中断矢量表
	IRQ_setVecs(vectors);
	//NMI中断使能
    	IRQ_nmiEnable();
    	//全局中断使能
    	IRQ_globalEnable();
   	for(i = 0; i < 0x80000; i++)
   	{
   		zbtsram_data[i] = 0;
   	}
	for(i = 0; i < 0x80000; i++)
	{
		zbtsram_data[i] = 0x12345678+i;
	}
	for(i = 0; i < 0x80000; i++)
	{
		if(zbtsram_data[i] != 0x12345678+i)
		{
			good_flag = 0;
			break;
		}
		good_flag = 1;
	}
	if(good_flag == 1)
	{
		printf("ZBTSRAM TEST IS OK!");
	}
	else
	{
		printf("ZBTSRAM TEST IS FAILED!");
	}
}