serial.tan.qmsg

利用VHDL语言编写的串口程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[7\] rxd_buf\[5\] 17.389 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[7\]\" through register \"rxd_buf\[5\]\" is 17.389 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.361 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 39; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "" { clk } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkbaud8x 2 REG LC_X8_Y10_N0 40 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N0; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "1.680 ns" { clk clkbaud8x } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.501 ns) + CELL(0.711 ns) 7.361 ns rxd_buf\[5\] 3 REG LC_X28_Y9_N0 11 " "Info: 3: + IC(3.501 ns) + CELL(0.711 ns) = 7.361 ns; Loc. = LC_X28_Y9_N0; Fanout = 11; REG Node = 'rxd_buf\[5\]'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "4.212 ns" { clkbaud8x rxd_buf[5] } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.32 % " "Info: Total cell delay = 3.115 ns ( 42.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.246 ns 57.68 % " "Info: Total interconnect delay = 4.246 ns ( 57.68 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "7.361 ns" { clk clkbaud8x rxd_buf[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.361 ns" { clk clk~out0 clkbaud8x rxd_buf[5] } { 0.000ns 0.000ns 0.745ns 3.501ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.804 ns + Longest register pin " "Info: + Longest register to pin delay is 9.804 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxd_buf\[5\] 1 REG LC_X28_Y9_N0 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y9_N0; Fanout = 11; REG Node = 'rxd_buf\[5\]'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "" { rxd_buf[5] } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.844 ns) + CELL(0.442 ns) 1.286 ns reduce_or~3176 2 COMB LC_X27_Y9_N0 2 " "Info: 2: + IC(0.844 ns) + CELL(0.442 ns) = 1.286 ns; Loc. = LC_X27_Y9_N0; Fanout = 2; COMB Node = 'reduce_or~3176'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "1.286 ns" { rxd_buf[5] reduce_or~3176 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.928 ns) + CELL(0.590 ns) 3.804 ns reduce_or~3177 3 COMB LC_X28_Y9_N9 6 " "Info: 3: + IC(1.928 ns) + CELL(0.590 ns) = 3.804 ns; Loc. = LC_X28_Y9_N9; Fanout = 6; COMB Node = 'reduce_or~3177'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "2.518 ns" { reduce_or~3176 reduce_or~3177 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.132 ns) + CELL(0.590 ns) 5.526 ns reduce_or~3200 4 COMB LC_X28_Y9_N5 1 " "Info: 4: + IC(1.132 ns) + CELL(0.590 ns) = 5.526 ns; Loc. = LC_X28_Y9_N5; Fanout = 1; COMB Node = 'reduce_or~3200'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "1.722 ns" { reduce_or~3177 reduce_or~3200 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.154 ns) + CELL(2.124 ns) 9.804 ns seg_data\[7\] 5 PIN PIN_139 0 " "Info: 5: + IC(2.154 ns) + CELL(2.124 ns) = 9.804 ns; Loc. = PIN_139; Fanout = 0; PIN Node = 'seg_data\[7\]'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "4.278 ns" { reduce_or~3200 seg_data[7] } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns 38.21 % " "Info: Total cell delay = 3.746 ns ( 38.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.058 ns 61.79 % " "Info: Total interconnect delay = 6.058 ns ( 61.79 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "9.804 ns" { rxd_buf[5] reduce_or~3176 reduce_or~3177 reduce_or~3200 seg_data[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.804 ns" { rxd_buf[5] reduce_or~3176 reduce_or~3177 reduce_or~3200 seg_data[7] } { 0.000ns 0.844ns 1.928ns 1.132ns 2.154ns } { 0.000ns 0.442ns 0.590ns 0.590ns 2.124ns } } }  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "7.361 ns" { clk clkbaud8x rxd_buf[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.361 ns" { clk clk~out0 clkbaud8x rxd_buf[5] } { 0.000ns 0.000ns 0.745ns 3.501ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "9.804 ns" { rxd_buf[5] reduce_or~3176 reduce_or~3177 reduce_or~3200 seg_data[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.804 ns" { rxd_buf[5] reduce_or~3176 reduce_or~3177 reduce_or~3200 seg_data[7] } { 0.000ns 0.844ns 1.928ns 1.132ns 2.154ns } { 0.000ns 0.442ns 0.590ns 0.590ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "rxd_reg1 rxd clk -1.809 ns register " "Info: th for register \"rxd_reg1\" (data pin = \"rxd\", clock pin = \"clk\") is -1.809 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.361 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 39; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "" { clk } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkbaud8x 2 REG LC_X8_Y10_N0 40 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N0; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "1.680 ns" { clk clkbaud8x } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.501 ns) + CELL(0.711 ns) 7.361 ns rxd_reg1 3 REG LC_X27_Y8_N3 2 " "Info: 3: + IC(3.501 ns) + CELL(0.711 ns) = 7.361 ns; Loc. = LC_X27_Y8_N3; Fanout = 2; REG Node = 'rxd_reg1'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "4.212 ns" { clkbaud8x rxd_reg1 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.32 % " "Info: Total cell delay = 3.115 ns ( 42.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.246 ns 57.68 % " "Info: Total interconnect delay = 4.246 ns ( 57.68 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "7.361 ns" { clk clkbaud8x rxd_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.361 ns" { clk clk~out0 clkbaud8x rxd_reg1 } { 0.000ns 0.000ns 0.745ns 3.501ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.185 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.185 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns rxd 1 PIN PIN_65 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_65; Fanout = 1; PIN Node = 'rxd'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "" { rxd } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.595 ns) + CELL(0.115 ns) 9.185 ns rxd_reg1 2 REG LC_X27_Y8_N3 2 " "Info: 2: + IC(7.595 ns) + CELL(0.115 ns) = 9.185 ns; Loc. = LC_X27_Y8_N3; Fanout = 2; REG Node = 'rxd_reg1'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "7.710 ns" { rxd rxd_reg1 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns 17.31 % " "Info: Total cell delay = 1.590 ns ( 17.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.595 ns 82.69 % " "Info: Total interconnect delay = 7.595 ns ( 82.69 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "9.185 ns" { rxd rxd_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.185 ns" { rxd rxd~out0 rxd_reg1 } { 0.000ns 0.000ns 7.595ns } { 0.000ns 1.475ns 0.115ns } } }  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "7.361 ns" { clk clkbaud8x rxd_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.361 ns" { clk clk~out0 clkbaud8x rxd_reg1 } { 0.000ns 0.000ns 0.745ns 3.501ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "9.185 ns" { rxd rxd_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.185 ns" { rxd rxd~out0 rxd_reg1 } { 0.000ns 0.000ns 7.595ns } { 0.000ns 1.475ns 0.115ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 07 21:58:20 2008 " "Info: Processing ended: Thu Feb 07 21:58:20 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}