serial.tan.qmsg

利用VHDL语言编写的串口程序

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "key_entry1 key_entry2 clk 3.315 ns " "Info: Found hold time violation between source  pin or register \"key_entry1\" and destination pin or register \"key_entry2\" for clock \"clk\" (Hold time is 3.315 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.447 ns + Largest " "Info: + Largest clock skew is 4.447 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.372 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 39; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "" { clk } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkbaud8x 2 REG LC_X8_Y10_N0 40 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N0; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "1.680 ns" { clk clkbaud8x } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.512 ns) + CELL(0.711 ns) 7.372 ns key_entry2 3 REG LC_X10_Y10_N6 18 " "Info: 3: + IC(3.512 ns) + CELL(0.711 ns) = 7.372 ns; Loc. = LC_X10_Y10_N6; Fanout = 18; REG Node = 'key_entry2'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "4.223 ns" { clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 55 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.25 % " "Info: Total cell delay = 3.115 ns ( 42.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.257 ns 57.75 % " "Info: Total interconnect delay = 4.257 ns ( 57.75 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "7.372 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.372 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.0ns 0.0ns 0.745ns 3.512ns } { 0.0ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.925 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 39; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "" { clk } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns key_entry1 2 REG LC_X11_Y10_N5 4 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X11_Y10_N5; Fanout = 4; REG Node = 'key_entry1'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "1.456 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "2.925 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 key_entry1 } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "7.372 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.372 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.0ns 0.0ns 0.745ns 3.512ns } { 0.0ns 1.469ns 0.935ns 0.711ns } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "2.925 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 key_entry1 } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.923 ns - Shortest register register " "Info: - Shortest register to register delay is 0.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_entry1 1 REG LC_X11_Y10_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y10_N5; Fanout = 4; REG Node = 'key_entry1'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "" { key_entry1 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.808 ns) + CELL(0.115 ns) 0.923 ns key_entry2 2 REG LC_X10_Y10_N6 18 " "Info: 2: + IC(0.808 ns) + CELL(0.115 ns) = 0.923 ns; Loc. = LC_X10_Y10_N6; Fanout = 18; REG Node = 'key_entry2'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "0.923 ns" { key_entry1 key_entry2 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 55 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 12.46 % " "Info: Total cell delay = 0.115 ns ( 12.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.808 ns 87.54 % " "Info: Total interconnect delay = 0.808 ns ( 87.54 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "0.923 ns" { key_entry1 key_entry2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.923 ns" { key_entry1 key_entry2 } { 0.0ns 0.808ns } { 0.0ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 55 -1 0 } }  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "7.372 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.372 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.0ns 0.0ns 0.745ns 3.512ns } { 0.0ns 1.469ns 0.935ns 0.711ns } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "2.925 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 key_entry1 } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "0.923 ns" { key_entry1 key_entry2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.923 ns" { key_entry1 key_entry2 } { 0.0ns 0.808ns } { 0.0ns 0.115ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "start_delaycnt key_input clk 6.945 ns register " "Info: tsu for register \"start_delaycnt\" (data pin = \"key_input\", clock pin = \"clk\") is 6.945 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.833 ns + Longest pin register " "Info: + Longest pin to register delay is 9.833 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key_input 1 PIN PIN_138 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_138; Fanout = 2; PIN Node = 'key_input'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "" { key_input } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.135 ns) + CELL(0.442 ns) 9.046 ns start_delaycnt~225 2 COMB LC_X11_Y10_N6 1 " "Info: 2: + IC(7.135 ns) + CELL(0.442 ns) = 9.046 ns; Loc. = LC_X11_Y10_N6; Fanout = 1; COMB Node = 'start_delaycnt~225'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "7.577 ns" { key_input start_delaycnt~225 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 9.342 ns start_delaycnt~226 3 COMB LC_X11_Y10_N7 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 9.342 ns; Loc. = LC_X11_Y10_N7; Fanout = 1; COMB Node = 'start_delaycnt~226'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "0.296 ns" { start_delaycnt~225 start_delaycnt~226 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 9.833 ns start_delaycnt 4 REG LC_X11_Y10_N8 21 " "Info: 4: + IC(0.182 ns) + CELL(0.309 ns) = 9.833 ns; Loc. = LC_X11_Y10_N8; Fanout = 21; REG Node = 'start_delaycnt'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "0.491 ns" { start_delaycnt~226 start_delaycnt } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.334 ns 23.74 % " "Info: Total cell delay = 2.334 ns ( 23.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.499 ns 76.26 % " "Info: Total interconnect delay = 7.499 ns ( 76.26 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "9.833 ns" { key_input start_delaycnt~225 start_delaycnt~226 start_delaycnt } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.833 ns" { key_input key_input~out0 start_delaycnt~225 start_delaycnt~226 start_delaycnt } { 0.000ns 0.000ns 7.135ns 0.182ns 0.182ns } { 0.000ns 1.469ns 0.442ns 0.114ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.925 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 39; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "" { clk } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns start_delaycnt 2 REG LC_X11_Y10_N8 21 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X11_Y10_N8; Fanout = 21; REG Node = 'start_delaycnt'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "1.456 ns" { clk start_delaycnt } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/serial.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "2.925 ns" { clk start_delaycnt } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 start_delaycnt } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "9.833 ns" { key_input start_delaycnt~225 start_delaycnt~226 start_delaycnt } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.833 ns" { key_input key_input~out0 start_delaycnt~225 start_delaycnt~226 start_delaycnt } { 0.000ns 0.000ns 7.135ns 0.182ns 0.182ns } { 0.000ns 1.469ns 0.442ns 0.114ns 0.309ns } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口实验/串口/" "" "2.925 ns" { clk start_delaycnt } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 start_delaycnt } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}