ledwater.tan.qmsg

使用VHDL语言编写的跑马灯程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[12\] register dataout_tmp\[7\] 208.9 MHz 4.787 ns Internal " "Info: Clock \"clk\" has Internal fmax of 208.9 MHz between source register \"cnt\[12\]\" and destination register \"dataout_tmp\[7\]\" (period= 4.787 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.526 ns + Longest register register " "Info: + Longest register to register delay is 4.526 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[12\] 1 REG LC_X11_Y3_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y3_N6; Fanout = 4; REG Node = 'cnt\[12\]'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "" { cnt[12] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.744 ns) + CELL(0.590 ns) 1.334 ns reduce_nor~179 2 COMB LC_X12_Y3_N8 1 " "Info: 2: + IC(0.744 ns) + CELL(0.590 ns) = 1.334 ns; Loc. = LC_X12_Y3_N8; Fanout = 1; COMB Node = 'reduce_nor~179'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "1.334 ns" { cnt[12] reduce_nor~179 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.150 ns) + CELL(0.442 ns) 2.926 ns reduce_nor~0 3 COMB LC_X12_Y2_N6 12 " "Info: 3: + IC(1.150 ns) + CELL(0.442 ns) = 2.926 ns; Loc. = LC_X12_Y2_N6; Fanout = 12; COMB Node = 'reduce_nor~0'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "1.592 ns" { reduce_nor~179 reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.867 ns) 4.526 ns dataout_tmp\[7\] 4 REG LC_X11_Y2_N9 2 " "Info: 4: + IC(0.733 ns) + CELL(0.867 ns) = 4.526 ns; Loc. = LC_X11_Y2_N9; Fanout = 2; REG Node = 'dataout_tmp\[7\]'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "1.600 ns" { reduce_nor~0 dataout_tmp[7] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.899 ns 41.96 % " "Info: Total cell delay = 1.899 ns ( 41.96 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.627 ns 58.04 % " "Info: Total interconnect delay = 2.627 ns ( 58.04 % )" {  } {  } 0}  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "4.526 ns" { cnt[12] reduce_nor~179 reduce_nor~0 dataout_tmp[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.526 ns" { cnt[12] reduce_nor~179 reduce_nor~0 dataout_tmp[7] } { 0.000ns 0.744ns 1.150ns 0.733ns } { 0.000ns 0.590ns 0.442ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.903 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 35; CLK Node = 'clk'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "" { clk } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns dataout_tmp\[7\] 2 REG LC_X11_Y2_N9 2 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X11_Y2_N9; Fanout = 2; REG Node = 'dataout_tmp\[7\]'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "1.434 ns" { clk dataout_tmp[7] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "2.903 ns" { clk dataout_tmp[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 dataout_tmp[7] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.903 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 35; CLK Node = 'clk'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "" { clk } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns cnt\[12\] 2 REG LC_X11_Y3_N6 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X11_Y3_N6; Fanout = 4; REG Node = 'cnt\[12\]'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "1.434 ns" { clk cnt[12] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "2.903 ns" { clk cnt[12] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cnt[12] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "2.903 ns" { clk dataout_tmp[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 dataout_tmp[7] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "2.903 ns" { clk cnt[12] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cnt[12] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } }  } 0}  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "4.526 ns" { cnt[12] reduce_nor~179 reduce_nor~0 dataout_tmp[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.526 ns" { cnt[12] reduce_nor~179 reduce_nor~0 dataout_tmp[7] } { 0.000ns 0.744ns 1.150ns 0.733ns } { 0.000ns 0.590ns 0.442ns 0.867ns } } } { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "2.903 ns" { clk dataout_tmp[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 dataout_tmp[7] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "2.903 ns" { clk cnt[12] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cnt[12] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[5\] dataout_tmp\[5\] 6.927 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[5\]\" through register \"dataout_tmp\[5\]\" is 6.927 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.903 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 35; CLK Node = 'clk'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "" { clk } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns dataout_tmp\[5\] 2 REG LC_X13_Y2_N5 2 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X13_Y2_N5; Fanout = 2; REG Node = 'dataout_tmp\[5\]'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "1.434 ns" { clk dataout_tmp[5] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "2.903 ns" { clk dataout_tmp[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 dataout_tmp[5] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest register pin " "Info: + Longest register to pin delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dataout_tmp\[5\] 1 REG LC_X13_Y2_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y2_N5; Fanout = 2; REG Node = 'dataout_tmp\[5\]'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "" { dataout_tmp[5] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.692 ns) + CELL(2.108 ns) 3.800 ns dataout\[5\] 2 PIN PIN_80 0 " "Info: 2: + IC(1.692 ns) + CELL(2.108 ns) = 3.800 ns; Loc. = PIN_80; Fanout = 0; PIN Node = 'dataout\[5\]'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "3.800 ns" { dataout_tmp[5] dataout[5] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 55.47 % " "Info: Total cell delay = 2.108 ns ( 55.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.692 ns 44.53 % " "Info: Total interconnect delay = 1.692 ns ( 44.53 % )" {  } {  } 0}  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "3.800 ns" { dataout_tmp[5] dataout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.800 ns" { dataout_tmp[5] dataout[5] } { 0.000ns 1.692ns } { 0.000ns 2.108ns } } }  } 0}  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "2.903 ns" { clk dataout_tmp[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 dataout_tmp[5] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "3.800 ns" { dataout_tmp[5] dataout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.800 ns" { dataout_tmp[5] dataout[5] } { 0.000ns 1.692ns } { 0.000ns 2.108ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 09 10:20:15 2008 " "Info: Processing ended: Wed Jul 09 10:20:15 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}