ledwater.map.qmsg

使用VHDL语言编写的跑马灯程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 09 10:20:21 2008 " "Info: Processing started: Wed Jul 09 10:20:21 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ledwater -c ledwater " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ledwater -c ledwater" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ledwater.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ledwater.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ledwater-arch " "Info: Found design unit 1: ledwater-arch" {  } { { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ledwater " "Info: Found entity 1: ledwater" {  } { { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ledwater " "Info: Elaborating entity \"ledwater\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "57 " "Info: Implemented 57 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "43 " "Info: Implemented 43 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 09 10:20:24 2008 " "Info: Processing ended: Wed Jul 09 10:20:24 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}