ledwater.tan.rpt

使用VHDL语言编写的跑马灯程序

; N/A                                     ; 243.25 MHz ( period = 4.111 ns )                    ; cnt[1]  ; dataout_tmp[2]  ; clk        ; clk      ; None                        ; None                      ; 3.850 ns                ;
; N/A                                     ; 247.22 MHz ( period = 4.045 ns )                    ; cnt[0]  ; dataout_tmp[10] ; clk        ; clk      ; None                        ; None                      ; 3.784 ns                ;
; N/A                                     ; 247.22 MHz ( period = 4.045 ns )                    ; cnt[0]  ; dataout_tmp[9]  ; clk        ; clk      ; None                        ; None                      ; 3.784 ns                ;
; N/A                                     ; 247.22 MHz ( period = 4.045 ns )                    ; cnt[0]  ; dataout_tmp[8]  ; clk        ; clk      ; None                        ; None                      ; 3.784 ns                ;
; N/A                                     ; 247.22 MHz ( period = 4.045 ns )                    ; cnt[0]  ; dataout_tmp[11] ; clk        ; clk      ; None                        ; None                      ; 3.784 ns                ;
; N/A                                     ; 247.22 MHz ( period = 4.045 ns )                    ; cnt[0]  ; dataout_tmp[6]  ; clk        ; clk      ; None                        ; None                      ; 3.784 ns                ;
; N/A                                     ; 247.22 MHz ( period = 4.045 ns )                    ; cnt[0]  ; dataout_tmp[1]  ; clk        ; clk      ; None                        ; None                      ; 3.784 ns                ;
; N/A                                     ; 247.22 MHz ( period = 4.045 ns )                    ; cnt[0]  ; dataout_tmp[0]  ; clk        ; clk      ; None                        ; None                      ; 3.784 ns                ;
; N/A                                     ; 247.46 MHz ( period = 4.041 ns )                    ; cnt[13] ; dataout_tmp[10] ; clk        ; clk      ; None                        ; None                      ; 3.780 ns                ;
; N/A                                     ; 247.46 MHz ( period = 4.041 ns )                    ; cnt[13] ; dataout_tmp[9]  ; clk        ; clk      ; None                        ; None                      ; 3.780 ns                ;
; N/A                                     ; 247.46 MHz ( period = 4.041 ns )                    ; cnt[13] ; dataout_tmp[8]  ; clk        ; clk      ; None                        ; None                      ; 3.780 ns                ;
; N/A                                     ; 247.46 MHz ( period = 4.041 ns )                    ; cnt[13] ; dataout_tmp[11] ; clk        ; clk      ; None                        ; None                      ; 3.780 ns                ;
; N/A                                     ; 247.46 MHz ( period = 4.041 ns )                    ; cnt[13] ; dataout_tmp[6]  ; clk        ; clk      ; None                        ; None                      ; 3.780 ns                ;
; N/A                                     ; 247.46 MHz ( period = 4.041 ns )                    ; cnt[13] ; dataout_tmp[1]  ; clk        ; clk      ; None                        ; None                      ; 3.780 ns                ;
; N/A                                     ; 247.46 MHz ( period = 4.041 ns )                    ; cnt[13] ; dataout_tmp[0]  ; clk        ; clk      ; None                        ; None                      ; 3.780 ns                ;
; N/A                                     ; 247.95 MHz ( period = 4.033 ns )                    ; cnt[3]  ; dataout_tmp[7]  ; clk        ; clk      ; None                        ; None                      ; 3.772 ns                ;
; N/A                                     ; 248.32 MHz ( period = 4.027 ns )                    ; cnt[3]  ; dataout_tmp[3]  ; clk        ; clk      ; None                        ; None                      ; 3.766 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;         ;                 ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------+
; tco                                                                            ;
+-------+--------------+------------+-----------------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From            ; To          ; From Clock ;
+-------+--------------+------------+-----------------+-------------+------------+
; N/A   ; None         ; 6.927 ns   ; dataout_tmp[5]  ; dataout[5]  ; clk        ;
; N/A   ; None         ; 6.906 ns   ; dataout_tmp[0]  ; dataout[0]  ; clk        ;
; N/A   ; None         ; 6.905 ns   ; dataout_tmp[10] ; dataout[10] ; clk        ;
; N/A   ; None         ; 6.903 ns   ; dataout_tmp[7]  ; dataout[7]  ; clk        ;
; N/A   ; None         ; 6.899 ns   ; dataout_tmp[8]  ; dataout[8]  ; clk        ;
; N/A   ; None         ; 6.896 ns   ; dataout_tmp[9]  ; dataout[9]  ; clk        ;
; N/A   ; None         ; 6.896 ns   ; dataout_tmp[6]  ; dataout[6]  ; clk        ;
; N/A   ; None         ; 6.892 ns   ; dataout_tmp[4]  ; dataout[4]  ; clk        ;
; N/A   ; None         ; 6.891 ns   ; dataout_tmp[11] ; dataout[11] ; clk        ;
; N/A   ; None         ; 6.605 ns   ; dataout_tmp[2]  ; dataout[2]  ; clk        ;
; N/A   ; None         ; 6.582 ns   ; dataout_tmp[3]  ; dataout[3]  ; clk        ;
; N/A   ; None         ; 6.579 ns   ; dataout_tmp[1]  ; dataout[1]  ; clk        ;
+-------+--------------+------------+-----------------+-------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Jul 09 10:20:15 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ledwater -c ledwater --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 208.9 MHz between source register "cnt[12]" and destination register "dataout_tmp[7]" (period= 4.787 ns)
    Info: + Longest register to register delay is 4.526 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y3_N6; Fanout = 4; REG Node = 'cnt[12]'
        Info: 2: + IC(0.744 ns) + CELL(0.590 ns) = 1.334 ns; Loc. = LC_X12_Y3_N8; Fanout = 1; COMB Node = 'reduce_nor~179'
        Info: 3: + IC(1.150 ns) + CELL(0.442 ns) = 2.926 ns; Loc. = LC_X12_Y2_N6; Fanout = 12; COMB Node = 'reduce_nor~0'
        Info: 4: + IC(0.733 ns) + CELL(0.867 ns) = 4.526 ns; Loc. = LC_X11_Y2_N9; Fanout = 2; REG Node = 'dataout_tmp[7]'
        Info: Total cell delay = 1.899 ns ( 41.96 % )
        Info: Total interconnect delay = 2.627 ns ( 58.04 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.903 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 35; CLK Node = 'clk'
            Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X11_Y2_N9; Fanout = 2; REG Node = 'dataout_tmp[7]'
            Info: Total cell delay = 2.180 ns ( 75.09 % )
            Info: Total interconnect delay = 0.723 ns ( 24.91 % )
        Info: - Longest clock path from clock "clk" to source register is 2.903 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 35; CLK Node = 'clk'
            Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X11_Y3_N6; Fanout = 4; REG Node = 'cnt[12]'
            Info: Total cell delay = 2.180 ns ( 75.09 % )
            Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "dataout[5]" through register "dataout_tmp[5]" is 6.927 ns
    Info: + Longest clock path from clock "clk" to source register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 35; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X13_Y2_N5; Fanout = 2; REG Node = 'dataout_tmp[5]'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y2_N5; Fanout = 2; REG Node = 'dataout_tmp[5]'
        Info: 2: + IC(1.692 ns) + CELL(2.108 ns) = 3.800 ns; Loc. = PIN_80; Fanout = 0; PIN Node = 'dataout[5]'
        Info: Total cell delay = 2.108 ns ( 55.47 % )
        Info: Total interconnect delay = 1.692 ns ( 44.53 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jul 09 10:20:15 2008
    Info: Elapsed time: 00:00:00