ads7822.v

来自「利用Verilog语言实现读取ADS7822模数转换芯片的串行输出数据」· Verilog 代码 · 共 86 行

//`timescale 1ns / 1ps
// synthesis translate_on
module ads7822 (
                   // inputs:
                    clk,
                    //read_n,
                    chipselect_n,
                    AD_DATA,
                  // outputs:
                    AD_CS,
                    AD_CLK,
                    irq,
                    //readdata
                 )
;
  input            clk;
  //input            read_n;
  input            chipselect_n;
  input           AD_DATA; 
  output           AD_CS;
  output           AD_CLK;
  output           irq;
  //output [15:0] readdata;
  
  
  
  wire             AD_DATA;
  reg            AD_CS;
  reg              AD_CLK;
  reg     [10:0]   DCLK_DIV;
  reg     [4:0]    COUNTER;
  reg     [15:0]   data_out;
  reg     [11:0]   data_reg;
  reg             irq;
  //wire    [15:0] readdata;

parameter CLK_FREQ = 'D50_000_000;
parameter DCLK_FREQ = 'D1_000_000;

 // assign readdata =  data_out;
 //assign AD_CS = chipselect_n;

always @(posedge clk)
  if(DCLK_DIV < (CLK_FREQ / DCLK_FREQ))
    DCLK_DIV <= DCLK_DIV+1;
  else
    begin 
      DCLK_DIV <= 0;
      AD_CLK <= ~AD_CLK;
    end



always @(negedge AD_CLK )
     
      
      
      
        if(COUNTER < 'd15)
         begin
         data_reg[0] <= AD_DATA;
         data_reg[11:1] <= data_reg[10:0];
         COUNTER <= COUNTER+1;
         
         end
       else if(COUNTER =='d15)
            begin
            COUNTER <= COUNTER+1;
            data_out <= {4'b0000,data_reg[11:0]};
            //
            AD_CS<= 1'b1;
            if(data_out<=2449)
                irq <= 1;
            else irq <= 0;
            end   
          else 
            begin
            COUNTER <= 0;
            AD_CS<= 1'b0;
            end
        

  //control_slave, which is an e_avalon_slave

endmodule