boot.asm

用于上位机对德州仪器的DSP的flash烧写

             .title  "Flash bootup utility for DM642 EVM"
             .option D,T
             .length 102
             .width  140
			 .sect ".boot_load"
			 .global _boot
_boot:
NORMAL_COPY_TABLE   .equ    0x90002000
;UPDATE_COPY_TABLE   .equ    0x90001000
EMIF_BASE           .equ    0x01800000

            
                  

   
;************************************************************************
;* Debug Loop -  Comment out B for Normal Operation
;************************************************************************

;            zero B1
;_myloop:  ; [!B1] B _myloop  
;            nop  5
;_myloopend: nop

;************************************************************************
;* Configure EMIF
;************************************************************************
		
        mvkl   emif_values, a3  ; load pointer to emif values
        mvkh   emif_values, a3
        
        mvkl   EMIF_BASE, a4    ; load EMIF base address
        mvkh   EMIF_BASE, a4

        mvkl   0x0009, b0       ; load number of registers to set
        mvkh   0x0000, b0

emif_loop:
        ldw    *a3++, b5        ; load register value
        sub    b0,1,b0          ; decrement counter
        nop    2
 [ b0]  b      emif_loop
        stw    b5, *a4++        ; store register value
        nop    4  

;****************************************************************************
;*Status Led reference
;****************************************************************************
		mvkl   0xa00c001f, a6
		mvkh   0xa00c001f, a6
		
		mvkl   0x3, a1
		mvkh   0x3, a1
		
		stb    a1, *a6
		
;****************************************************************************
;* Copy code sections
;****************************************************************************
        mvkl   0x9007ffff, a6
        mvkh   0x9007ffff, a6
        
        mvkl   0xa0000019, b4   ; load cpld address
        mvkh   0xa0000019, b4   
        
;        mvkl   0x903ff004, a3   ;bootloader switch
;        mvkh   0x903ff004, a3
        
;        shru   a3, 19, a1	    ;flash page select	
;        and    a1, 0x0000000f, a1
;        stb    a1, *b4
;        and    a6, a3, a2
        
;        ldh    *a2, a1
;        nop    4
;        cmpeq  a1, 0x0, b0
;  [b0]	mvkl   UPDATE_COPY_TABLE, a3     ; load table pointer 
;  [b0]	mvkh   UPDATE_COPY_TABLE, a3
;  [!b0] mvkl   NORMAL_COPY_TABLE, a3
;  [!b0] mvkh   NORMAL_COPY_TABLE, a3

		mvkl   NORMAL_COPY_TABLE, a3
		mvkh   NORMAL_COPY_TABLE, a3
				
        shru   a3, 19, a1	    ;flash page select	
        and    a1, 0x0000000f, a1
        stb    a1, *b4
        
        and    a6, a3, a2		; Load entry point
        ldw    *a2, b1       
		add    a3, 4, a3
		nop    3
copy_section_top:
        shru   a3, 19, a1       ;flash page select
        and    a1, 0x0000000f, a1
		stb    a1, *b4
		
		and    a6, a3, a2      
		ldw    *a2, b0 		    ; bytes count
        add    a3, 4, a3
        nop    3        
        
        shru   a3, 19, a1       ;flash page select
        and    a1, 0xf, a1
		stb    a1, *b4
		
		and    a6, a3, a2
		ldw    *a2, a4		    ; ram start address
		add    a3, 4, a3      
        nop    3

 [!b0]  b      copy_done        ;have we copied all sections?
        nop    5

copy_loop:
        shru   a3, 19, a1       ;flash page select
        and    a1, 0xf, a1
		stb    a1, *b4
		and    a6, a3, a2
		ldh    *a2, b5
		add    a3, 2, a3
        sub    b0,2,b0           ;decrement counter
        
        cmpeq  b0, 1, b2
 [ b2]  add    b0, 1, b0
 
 [ b0]  b      copy_loop         ;setup branch if not done
 [!b0]  b      copy_section_top
        zero   a1
 [!b0]  and    3,a3,a1
        sth    b5,*a4++
 [!b0]  and    -4,a3,a5          ;round address up to next multiple of 4
 [ a1]  add    4,a5,a3           ;round address up to next multiple of 4

;****************************************************************************
;* Jump to entry point
;****************************************************************************
copy_done:
        b    .S2 b1
        nop   5
	
emif_values:
        .long 0x00052078      ; GBLCTL
        .long 0x73a28e11      ; CECTL1 (Flash/FPGA)
        .long 0xffffffd3      ; CECTL0 (SDRAM)
        .long 0x00000000
        .long 0x22a28a02      ; CECTL2
        .long 0x22a28a22      ; CECTL3
        .long 0x53115000      ; SDCTL
        .long 0x0000081b      ; SDTIM (refresh period)
        .long 0x001faf4d      ; SDEXT