📄 config.asm
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;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,A0
;* ZERO B5
;* ZERO B4
;* MV A0,A1
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C112:
;* 0 [ A0] LDW .D2T2 *+SP(4),B5 ; |588| ^
;* 1 NOP 4
;* 5 ADD .D2 1,B5,B7 ; |588| ^
;* 6 [ A1] STW .D2T2 B7,*+SP(4) ; |588| ^
;* 7 [ A1] LDW .D2T2 *+SP(4),B4 ; |589| ^
;* 8 NOP 4
;* 12 CMPLT .L2 B4,B6,B0 ; |589| ^
;* 13 [!B0] ZERO .D1 A0 ; ^
;* 14 [ B0] B .S1 C112 ; |589|
;* 15 NOP 3
;* 18 MV .D1 A0,A3 ; Split a long life
;* 19 MV .D1 A3,A1 ; Split a long life
;* ; BRANCH OCCURS ; |589|
;*----------------------------------------------------------------------------*
L10: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L11: ; PIPED LOOP KERNEL
[ A1] STW .D2T2 B7,*+SP(4) ; |588| <0,6> ^
[ A1] LDW .D2T2 *+SP(4),B4 ; |589| <0,7> ^
NOP 4
CMPLT .L2 B4,B6,B0 ; |589| <0,12> ^
[!B0] ZERO .D1 A0 ; <0,13> ^
[ B0] BNOP .S1 L11,3 ; |589| <0,14>
|| [ A0] LDW .D2T2 *+SP(4),B5 ; |588| <1,0> ^
MV .D1 A0,A3 ; <0,18> Split a long life
MV .D1 A3,A1 ; <0,19> Split a long life
|| ADD .D2 1,B5,B7 ; |588| <1,5> ^
;** --------------------------------------------------------------------------*
L12: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
MV .D2 B6,B10
;** --------------------------------------------------------------------------*
L13:
MVKL .S2 _Phocus1820_flash_write,B5 ; |591|
MVKH .S2 _Phocus1820_flash_write,B5 ; |591|
CALL .S2 B5 ; |591|
ZERO .D1 A4 ; |591|
ADDKPC .S2 RL21,B3,0 ; |591|
MVKH .S1 0x90080000,A4 ; |591|
MV .D2X A14,B4 ; |591|
MV .D1 A13,A6 ; |591|
RL21: ; CALL OCCURS ; |591|
MV .D1 A4,A0 ; |591|
[ A0] BNOP .S1 L18,3 ; |591|
MVKL .S2 _Phocus1820_write_mode_info,B4 ; |594|
MV .D1 A11,A4 ; |594|
|| MVKH .S2 _Phocus1820_write_mode_info,B4 ; |594|
|| MVK .S1 55,A3 ; |593|
|| MVK .L1 1,A5 ; |593|
|| ZERO .D2 B11 ; |596|
; BRANCH OCCURS ; |591|
;** --------------------------------------------------------------------------*
CALL .S2 B4 ; |594|
ADDKPC .S2 RL22,B3,1 ; |594|
STH .D1T1 A5,*+A10[A3] ; |593|
NOP 2
RL22: ; CALL OCCURS ; |594|
STW .D2T2 B11,*+SP(4) ; |596|
LDW .D2T2 *+SP(4),B4 ; |597|
NOP 4
CMPLT .L2 B4,B10,B0 ; |597|
[!B0] B .S1 L17 ; |597|
[ B0] LDW .D2T2 *+SP(4),B5 ; |599| (P) <0,0> ^
|| [!B0] MVKL .S2 _Phocus1820_read_mode_info,B4 ; |602|
NOP 2
[!B0] MVKH .S2 _Phocus1820_read_mode_info,B4 ; |602|
[ B0] MVK .D1 0x1,A0
; BRANCH OCCURS ; |597|
;** --------------------------------------------------------------------------*
ZERO .D2 B4
|| MV .S2 B10,B6
|| MV .D1 A0,A1
|| ADD .L2 1,B5,B7 ; |599| (P) <0,5> ^
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 597
;* Loop opening brace source line : 598
;* Loop closing brace source line : 600
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 14
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 3
;* Resource Partition:
;* A-side B-side
;* .L units 0 1
;* .S units 1 0
;* .D units 0 3*
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 0 3*
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 3 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2 2
;*
;* Searching for software pipeline schedule at ...
;* ii = 14 Schedule found with 2 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |** | **** * |
;* 1: |** | *** * |
;* 2: |* | *** * |
;* 3: |* | *** * |
;* 4: |* | *** * |
;* 5: |* | *** * |
;* 6: |* | *** * |
;* 7: |* |* *** * |
;* 8: |* |* *** * |
;* 9: |* | *** * |
;* 10: |* | *** * |
;* 11: |* | *** * |
;* 12: |* | *** * |
;* 13: |* * | *** * |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop is interruptible
;* Collapsed epilog stages : 1
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,A0
;* ZERO B5
;* ZERO B4
;* MV A0,A1
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C90:
;* 0 [ A0] LDW .D2T2 *+SP(4),B5 ; |599| ^
;* 1 NOP 4
;* 5 ADD .D2 1,B5,B7 ; |599| ^
;* 6 [ A1] STW .D2T2 B7,*+SP(4) ; |599| ^
;* 7 [ A1] LDW .D2T2 *+SP(4),B4 ; |600| ^
;* 8 NOP 4
;* 12 CMPLT .L2 B4,B6,B0 ; |600| ^
;* 13 [!B0] ZERO .D1 A0 ; ^
;* 14 [ B0] B .S1 C90 ; |600|
;* 15 NOP 3
;* 18 MV .D1 A0,A3 ; Split a long life
;* 19 MV .D1 A3,A1 ; Split a long life
;* ; BRANCH OCCURS ; |600|
;*----------------------------------------------------------------------------*
L14: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L15: ; PIPED LOOP KERNEL
[ A1] STW .D2T2 B7,*+SP(4) ; |599| <0,6> ^
[ A1] LDW .D2T2 *+SP(4),B4 ; |600| <0,7> ^
NOP 4
CMPLT .L2 B4,B6,B0 ; |600| <0,12> ^
[!B0] ZERO .D1 A0 ; <0,13> ^
[ B0] BNOP .S1 L15,3 ; |600| <0,14>
|| [ A0] LDW .D2T2 *+SP(4),B5 ; |599| <1,0> ^
MV .D1 A0,A3 ; <0,18> Split a long life
MV .D1 A3,A1 ; <0,19> Split a long life
|| ADD .D2 1,B5,B7 ; |599| <1,5> ^
;** --------------------------------------------------------------------------*
L16: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
MVKL .S2 _Phocus1820_read_mode_info,B4 ; |602|
MVKH .S2 _Phocus1820_read_mode_info,B4 ; |602|
;** --------------------------------------------------------------------------*
L17:
CALL .S2 B4 ; |602|
ADDKPC .S2 RL23,B3,3 ; |602|
MV .D1 A11,A4 ; |602|
RL23: ; CALL OCCURS ; |602|
MVK .S1 55,A3 ; |603|
LDHU .D1T1 *+A10[A3],A3 ; |603|
NOP 4
CMPEQ .L1 A3,1,A0 ; |603|
[ A0] MVC .S2 CSR,B4 ; |269|
[ A0] OR .D2 1,B4,B4 ; |269|
[ A0] MVC .S2 B4,CSR ; |269|
[ A0] BNOP .S1 L19,3 ; |606|
[ A0] ZERO .S1 A12 ; |606|
|| [ A0] MV .D1X SP,A31 ; |612|
[ A0] LDDW .D1T1 *+A31(16),A11:A10 ; |612|
|| [ A0] LDDW .D2T2 *+SP(32),B11:B10 ; |612|
|| [ A0] MV .S2 B13,B3 ; |612|
; BRANCH OCCURS ; |606|
;** --------------------------------------------------------------------------*
L18:
MVC .S2 CSR,B4 ; |269|
OR .D2 1,B4,B4 ; |269|
MVC .S2 B4,CSR ; |269|
MVK .D1 0x7,A12 ; |610|
MV .D1X SP,A31 ; |612|
LDDW .D1T1 *+A31(16),A11:A10 ; |612|
|| LDDW .D2T2 *+SP(32),B11:B10 ; |612|
|| MV .S2 B13,B3 ; |612|
;** --------------------------------------------------------------------------*
L19:
RET .S2 B3 ; |612|
|| LDDW .D1T1 *+A31(24),A13:A12 ; |612|
|| LDW .D2T2 *+SP(12),B13 ; |612|
|| MV .S1 A12,A4 ; |610|
LDW .D2T1 *++SP(40),A14 ; |612|
NOP 4
; BRANCH OCCURS ; |612|
.sect ".text"
;******************************************************************************
;* FUNCTION NAME: _PostProcess(int, int, _tagImageInfo *, char **, int *) *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,B0,*
;* B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,SP, *
;* A16,A17,A18,A19,A20,A21,A22,A23,A24,A25,A26,A27, *
;* A28,A29,A30,A31,B16,B17,B18,B19,B20,B21,B22,B23, *
;* B24,B25,B26,B27,B28,B29,B30,B31 *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,B0,*
;* B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,SP, *
;* A16,A17,A18,A19,A20,A21,A22,A23,A24,A25,A26,A27, *
;* A28,A29,A30,A31,B16,B17,B18,B19,B20,B21,B22,B23, *
;* B24,B25,B26,B27,B28,B29,B30,B31 *
;* Local Frame Size : 0 Args + 0 Auto + 40 Save = 40 byte *
;******************************************************************************
_PostProcess__FiT1P13_tagImageInfoPPcPi:
;** --------------------------------------------------------------------------*
CMPEQ .L1 A4,1,A0 ; |783|
[ A0] BNOP .S1 L23,1 ; |783|
STW .D2T1 A14,*SP--(40) ; |778|
|| MV .D1X SP,A31 ; |778|
STDW .D2T2 B13:B12,*+SP(32)
|| MV .D1X B4,A5 ; |778|
STDW .D2T2 B11:B10,*+SP(24)
|| STDW .D1T1 A13:A12,*-A31(24)
|| MV .S1X B4,A3 ; |778|
|| CMPEQ .L2X A4,5,B0 ; |825|
STW .D2T2 B3,*+SP(4)
|| MV .S1X B6,A10 ; |778|
|| MV .L1 A6,A12 ; |778|
|| STDW .D1T1 A11:A10,*-A31(32)
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