📄 config.asm
字号:
|| MV .D1 A10,A4
NOP 4
; BRANCH OCCURS ; |117|
.sect ".text"
.global _UpdateProgram__10CConfigureFPci
;******************************************************************************
;* FUNCTION NAME: CConfigure::_UpdateProgram(char *, int) *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,B0,*
;* B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B13,SP,A16, *
;* A17,A18,A19,A20,A21,A22,A23,A24,A25,A26,A27,A28, *
;* A29,A30,A31,B16,B17,B18,B19,B20,B21,B22,B23,B24, *
;* B25,B26,B27,B28,B29,B30,B31 *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,B0,*
;* B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B13,DP,SP,A16,*
;* A17,A18,A19,A20,A21,A22,A23,A24,A25,A26,A27,A28, *
;* A29,A30,A31,B16,B17,B18,B19,B20,B21,B22,B23,B24, *
;* B25,B26,B27,B28,B29,B30,B31 *
;* Local Frame Size : 0 Args + 4 Auto + 32 Save = 36 byte *
;******************************************************************************
_UpdateProgram__10CConfigureFPci:
;** --------------------------------------------------------------------------*
MVKL .S1 _Phocus1820_write_mode_info,A3 ; |568|
MVKH .S1 _Phocus1820_write_mode_info,A3 ; |568|
MV .D1X SP,A31 ; |564|
CALL .S2X A3 ; |568|
STW .D2T1 A14,*SP--(40) ; |564|
STDW .D1T1 A11:A10,*-A31(24)
|| MVK .S1 110,A5 ; |568|
STDW .D1T1 A13:A12,*-A31(16)
|| STDW .D2T2 B11:B10,*+SP(32)
|| MV .L1X B4,A14 ; |564|
|| MVK .S1 55,A7 ; |567|
|| ZERO .S2 B5 ; |565|
MVK .D1 2,A4 ; |567|
|| ADD .S1 A5,A4,A11 ; |568|
|| MV .L1 A4,A10 ; |564|
|| STW .D2T2 B5,*+SP(4) ; |565|
ADDKPC .S2 RL18,B3,0 ; |568|
|| MV .S1 A11,A4 ; |568|
|| STH .D1T1 A4,*+A10[A7] ; |567|
|| MV .L2 B3,B13
|| STW .D2T2 B13,*+SP(12)
|| MV .L1 A6,A13 ; |564|
RL18: ; CALL OCCURS ; |568|
LDW .D2T2 *+SP(4),B5 ; |570|
NOP 2
MVKL .S2 0x7a120,B4 ; |570|
MVKH .S2 0x7a120,B4 ; |570|
CMPLT .L2 B5,B4,B0 ; |570|
[!B0] B .S1 L9 ; |570|
MVKL .S2 0x7a120,B10 ; |570|
[ B0] LDW .D2T2 *+SP(4),B5 ; |572| (P) <0,0> ^
|| MVKH .S2 0x7a120,B10 ; |570|
NOP 1
[!B0] MVKL .S2 _Phocus1820_read_mode_info,B4 ; |575|
[!B0] MVKH .S2 _Phocus1820_read_mode_info,B4 ; |575|
; BRANCH OCCURS ; |570|
;** --------------------------------------------------------------------------*
MVK .D1 0x1,A0
ZERO .D2 B4
|| MV .S2 B10,B6
|| MV .D1 A0,A1
|| ADD .L2 1,B5,B7 ; |572| (P) <0,5> ^
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 570
;* Loop opening brace source line : 571
;* Loop closing brace source line : 573
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 14
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 3
;* Resource Partition:
;* A-side B-side
;* .L units 0 1
;* .S units 1 0
;* .D units 0 3*
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 0 3*
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 3 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2 2
;*
;* Searching for software pipeline schedule at ...
;* ii = 14 Schedule found with 2 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |** | **** * |
;* 1: |** | *** * |
;* 2: |* | *** * |
;* 3: |* | *** * |
;* 4: |* | *** * |
;* 5: |* | *** * |
;* 6: |* | *** * |
;* 7: |* |* *** * |
;* 8: |* |* *** * |
;* 9: |* | *** * |
;* 10: |* | *** * |
;* 11: |* | *** * |
;* 12: |* | *** * |
;* 13: |* * | *** * |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop is interruptible
;* Collapsed epilog stages : 1
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,A0
;* ZERO B5
;* ZERO B4
;* MV A0,A1
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C134:
;* 0 [ A0] LDW .D2T2 *+SP(4),B5 ; |572| ^
;* 1 NOP 4
;* 5 ADD .D2 1,B5,B7 ; |572| ^
;* 6 [ A1] STW .D2T2 B7,*+SP(4) ; |572| ^
;* 7 [ A1] LDW .D2T2 *+SP(4),B4 ; |573| ^
;* 8 NOP 4
;* 12 CMPLT .L2 B4,B6,B0 ; |573| ^
;* 13 [!B0] ZERO .D1 A0 ; ^
;* 14 [ B0] B .S1 C134 ; |573|
;* 15 NOP 3
;* 18 MV .D1 A0,A3 ; Split a long life
;* 19 MV .D1 A3,A1 ; Split a long life
;* ; BRANCH OCCURS ; |573|
;*----------------------------------------------------------------------------*
L6: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L7: ; PIPED LOOP KERNEL
[ A1] STW .D2T2 B7,*+SP(4) ; |572| <0,6> ^
[ A1] LDW .D2T2 *+SP(4),B4 ; |573| <0,7> ^
NOP 4
CMPLT .L2 B4,B6,B0 ; |573| <0,12> ^
[!B0] ZERO .D1 A0 ; <0,13> ^
[ B0] BNOP .S1 L7,3 ; |573| <0,14>
|| [ A0] LDW .D2T2 *+SP(4),B5 ; |572| <1,0> ^
MV .D1 A0,A3 ; <0,18> Split a long life
MV .D1 A3,A1 ; <0,19> Split a long life
|| ADD .D2 1,B5,B7 ; |572| <1,5> ^
;** --------------------------------------------------------------------------*
L8: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
MV .D2 B6,B10
MVKL .S2 _Phocus1820_read_mode_info,B4 ; |575|
MVKH .S2 _Phocus1820_read_mode_info,B4 ; |575|
;** --------------------------------------------------------------------------*
L9:
CALL .S2 B4 ; |575|
ADDKPC .S2 RL19,B3,3 ; |575|
MV .D1 A11,A4 ; |575|
RL19: ; CALL OCCURS ; |575|
MVK .S1 55,A3 ; |576|
LDHU .D1T1 *+A10[A3],A3 ; |576|
NOP 3
MVK .S1 0x7,A12 ; |578|
CMPEQ .L1 A3,2,A0 ; |576|
[!A0] BNOP .S1 L19,3 ; |578|
[!A0] MV .D1X SP,A31 ; |612|
[!A0] LDDW .D1T1 *+A31(16),A11:A10 ; |612|
|| [!A0] LDDW .D2T2 *+SP(32),B11:B10 ; |612|
|| [!A0] MV .S2 B13,B3 ; |612|
; BRANCH OCCURS ; |578|
;** --------------------------------------------------------------------------*
MVC .S2 CSR,B4 ; |274|
AND .D2 -2,B4,B4 ; |274|
MVC .S2 B4,CSR ; |274|
MVKL .S1 _Phocus1820_flash_erase,A3 ; |583|
MVKH .S1 _Phocus1820_flash_erase,A3 ; |583|
ZERO .D2 B4 ; |583|
CALL .S2X A3 ; |583|
MVKH .S2 0x400000,B4 ; |583|
ZERO .D1 A4 ; |583|
ADDKPC .S2 RL20,B3,1 ; |583|
MVKH .S1 0x90080000,A4 ; |583|
RL20: ; CALL OCCURS ; |583|
ZERO .D2 B4 ; |585|
STW .D2T2 B4,*+SP(4) ; |585|
LDW .D2T2 *+SP(4),B4 ; |586|
NOP 4
CMPLT .L2 B4,B10,B0 ; |586|
[!B0] BNOP .S1 L13,4 ; |586|
[ B0] LDW .D2T2 *+SP(4),B5 ; |588| (P) <0,0> ^
; BRANCH OCCURS ; |586|
;** --------------------------------------------------------------------------*
MVK .D1 0x1,A0
ZERO .D2 B4
MV .S2 B10,B6
MV .D1 A0,A1
ADD .L2 1,B5,B7 ; |588| (P) <0,5> ^
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 586
;* Loop opening brace source line : 587
;* Loop closing brace source line : 589
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 14
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 3
;* Resource Partition:
;* A-side B-side
;* .L units 0 1
;* .S units 1 0
;* .D units 0 3*
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 0 3*
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 3 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2 2
;*
;* Searching for software pipeline schedule at ...
;* ii = 14 Schedule found with 2 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |** | **** * |
;* 1: |** | *** * |
;* 2: |* | *** * |
;* 3: |* | *** * |
;* 4: |* | *** * |
;* 5: |* | *** * |
;* 6: |* | *** * |
;* 7: |* |* *** * |
;* 8: |* |* *** * |
;* 9: |* | *** * |
;* 10: |* | *** * |
;* 11: |* | *** * |
;* 12: |* | *** * |
;* 13: |* * | *** * |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop is interruptible
;* Collapsed epilog stages : 1
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
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