📄 net.asm
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|| [ A0] B .S2 L21 ; |225|
MVKL .S1 _nMainConfigSize,A11 ; |230|
MVKL .S2 _CfgSave,B7 ; |229|
|| MVKH .S1 _nMainConfigSize,A3 ; |229|
MVKL .S2 _nMainConfigSize,B5 ; |228|
|| MVK .S1 512,A14 ; |230|
MVKH .S2 _CfgSave,B7 ; |229|
|| MVKH .S1 _nMainConfigSize,A11 ; |230|
MVKH .S2 _nMainConfigSize,B5 ; |228|
|| ZERO .L1 A6 ; |229|
|| ZERO .L2 B6 ; |228|
|| MV .S1 A3,A13 ; |229|
|| MV .D2X A3,B4 ; |229|
|| MV .D1 A12,A4 ; |229|
; BRANCH OCCURS ; |225|
;** --------------------------------------------------------------------------*
CALL .S2 B7 ; |229|
ADDKPC .S2 RL12,B3,1 ; |229|
STW .D2T2 B6,*B5 ; |228|
NOP 2
RL12: ; CALL OCCURS ; |229|
LDW .D1T1 *A11,A3 ; |230|
NOP 1
MVKL .S2 _strMainConfig,B6 ; |241|
MV .S1 A12,A4 ; |241|
MV .D2X A13,B4 ; |229|
CMPGTU .L1 A3,A14,A0 ; |230|
[ A0] B .S1 L19 ; |230|
MVKL .S2 _CfgFree,B5 ; |235|
MVKH .S2 _strMainConfig,B6 ; |241|
MVKL .S2 _CfgSave,B7 ; |241|
MV .D1X B6,A6 ; |241|
|| MVKH .S2 _CfgFree,B5 ; |235|
MV .D1X B6,A11 ; |241|
|| MVKH .S2 _CfgSave,B7 ; |241|
; BRANCH OCCURS ; |230|
;** --------------------------------------------------------------------------*
CALL .S2 B7 ; |241|
ADDKPC .S2 RL13,B3,4 ; |241|
RL13: ; CALL OCCURS ; |241|
CMPGT .L1 A4,0,A0 ; |241|
[!A0] B .S1 L23 ; |241|
MVKL .S2 _CfgFree,B4 ; |242|
MVK .S2 0x28,B11 ; |212|
MV .D1 A12,A4 ; |242|
|| MVKH .S2 _CfgFree,B4 ; |242|
|| MV .L1 A11,A13 ; |241|
|| MVK .S1 0x50,A14 ; |173|
[!A0] MVKL .S1 _NC_SystemClose,A3 ; |310|
[!A0] MVKH .S1 _NC_SystemClose,A3 ; |310|
; BRANCH OCCURS ; |241|
;** --------------------------------------------------------------------------*
CALL .S2 B4 ; |242|
ADDKPC .S2 RL14,B3,4 ; |242|
RL14: ; CALL OCCURS ; |242|
MVKL .S1 _CfgNew,A3 ; |253|
MVKH .S1 _CfgNew,A3 ; |253|
NOP 1
;** --------------------------------------------------------------------------*
;** BEGIN LOOP L11
;** --------------------------------------------------------------------------*
L11:
CALL .S2X A3 ; |253|
ADDKPC .S2 RL15,B3,4 ; |253|
RL15: ; CALL OCCURS ; |253|
MV .D1 A4,A0 ; |253|
[!A0] B .S1 L24 ; |259|
MV .D1 A4,A12 ; |253|
|| [ A0] MVKL .S2 _CfgLoad,B5 ; |262|
|| [ A0] MVKL .S1 _nMainConfigSize,A3 ; |262|
[ A0] MVKH .S2 _CfgLoad,B5 ; |262|
|| [ A0] MVKH .S1 _nMainConfigSize,A3 ; |262|
[!A0] MVKL .S1 _NC_SystemClose,A3 ; |310|
[!A0] MVKH .S1 _NC_SystemClose,A3 ; |310|
NOP 1
; BRANCH OCCURS ; |259|
;** --------------------------------------------------------------------------*
CALL .S2 B5 ; |262|
|| LDW .D1T1 *A3,A11 ; |262|
ADDKPC .S2 RL16,B3,2 ; |262|
MV .D1 A13,A6 ; |262|
MV .D2X A11,B4 ; |262|
RL16: ; CALL OCCURS ; |262|
CMPEQ .L1 A4,A11,A0 ; |262|
[!A0] BNOP .S1 L21,2 ; |262|
[ A0] MVKL .S1 _g_nDhcpEnable,A3 ; |264|
[ A0] MVKH .S1 _g_nDhcpEnable,A3 ; |264|
[ A0] LDW .D1T1 *A3,A3 ; |264|
; BRANCH OCCURS ; |262|
;** --------------------------------------------------------------------------*
NOP 4
CMPEQ .L1 A3,1,A0 ; |264|
[ A0] BNOP .S1 L17,1 ; |264|
[!A0] MVKL .S2 _mmZeroInit,B5 ; |280|
[!A0] MVKH .S2 _mmZeroInit,B5 ; |280|
[ A0] MVKL .S2 _mmZeroInit,B5 ; |269|
[ A0] MVKH .S2 _mmZeroInit,B5 ; |269|
; BRANCH OCCURS ; |264|
;** --------------------------------------------------------------------------*
CALL .S2 B5 ; |280|
ADDAW .D2 SP,15,B6 ; |280|
ADDKPC .S2 RL17,B3,1 ; |280|
MV .D1X B6,A4 ; |280|
MV .D2X A14,B4 ; |280|
RL17: ; CALL OCCURS ; |280|
MVKL .S1 _inet_addr,A3 ; |281|
MVKL .S2 _g_pEthInfo,B4 ; |281|
|| MVKH .S1 _inet_addr,A3 ; |281|
MVKH .S2 _g_pEthInfo,B4 ; |281|
CALL .S2X A3 ; |281|
LDW .D2T1 *B4,A4 ; |281|
ADDKPC .S2 RL18,B3,3 ; |281|
RL18: ; CALL OCCURS ; |281|
MVKL .S2 _inet_addr,B4 ; |282|
MVKH .S2 _inet_addr,B4 ; |282|
CALL .S2 B4 ; |282|
MV .D1 A4,A3 ; |281|
STW .D2T1 A3,*+SP(64) ; |281|
ADDKPC .S2 RL19,B3,0 ; |282|
MVKL .S1 SL3+0,A4 ; |282|
MVKH .S1 SL3+0,A4 ; |282|
RL19: ; CALL OCCURS ; |282|
MVKL .S1 _g_pEthInfo,A3 ; |186|
MVKH .S1 _g_pEthInfo,A3 ; |186|
LDW .D1T1 *A3,A3 ; |186|
NOP 2
STW .D2T1 A4,*+SP(68) ; |282|
ADDAW .D2 SP,19,B4 ; |186|
ADDAW .D1 A3,15,A3 ; |186|
LDB .D1T1 *A3,A0 ; |186|
NOP 3
MV .D1X B4,A4 ; |186|
[!A0] BNOP .S1 L15,1 ; |186|
[!A0] MVKL .S2 _CfgAddEntry,B5 ; |288|
STB .D1T1 A0,*A4 ; |186|
[!A0] MVKH .S2 _CfgAddEntry,B5 ; |288|
[ A0] LDB .D1T1 *++A3,A0 ; |186| (P) <0,0> ^
; BRANCH OCCURS ; |186|
;** --------------------------------------------------------------------------*
NOP 2
MVK .D2 0x1,B0
MV .D2 B0,B1
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 186
;* Loop closing brace source line : 186
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 6
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 0 1
;* .D units 2* 0
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 2* 0
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 0 4 (.L or .S or .D unit)
;* Bound(.L .S .LS) 0 1
;* Bound(.L .S .D .LS .LSD) 1 2*
;*
;* Searching for software pipeline schedule at ...
;* ii = 6 Schedule found with 2 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |* ** |** |
;* 1: |* ** |* |
;* 2: |* ** |* |
;* 3: |* ** |* |
;* 4: |* ** |* * |
;* 5: |* ** |* * |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop is interruptible
;* Collapsed epilog stages : 1
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* For further improvement on this loop, try option -mh14
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,B0
;* ZERO A0
;* MV B0,B1
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C63:
;* 0 [ B0] LDB .D1T1 *++A3,A0 ; |186| ^
;* 1 NOP 4
;* 5 [ B1] STB .D1T1 A0,*++A4 ; |186| ^
;* || [!A0] ZERO .D2 B0 ; ^
;* || [ A0] B .S2 C63 ; |186|
;* 6 NOP 2
;* 8 MV .D2 B0,B4 ; Split a long life
;* 9 NOP 1
;* 10 MV .D2 B4,B1 ; Split a long life
;* ; BRANCH OCCURS ; |186|
;*----------------------------------------------------------------------------*
L12: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L13: ; PIPED LOOP KERNEL
[ A0] B .S2 L13 ; |186| <0,5>
|| [ B1] STB .D1T1 A0,*++A4 ; |186| <0,5> ^
|| [!A0] ZERO .D2 B0 ; <0,5> ^
[ B0] LDB .D1T1 *++A3,A0 ; |186| <1,0> ^
NOP 1
MV .D2 B0,B4 ; <0,8> Split a long life
NOP 1
MV .D2 B4,B1 ; <0,10> Split a long life
;** --------------------------------------------------------------------------*
L14: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
MVKL .S2 _CfgAddEntry,B5 ; |288|
MVKH .S2 _CfgAddEntry,B5 ; |288|
;** --------------------------------------------------------------------------*
L15:
CALL .S2 B5 ; |288|
MVK .S2 0x4,B4 ; |288|
ADDAW .D2 SP,15,B8 ; |288|
ZERO .L2 B12 ; |284|
ADDKPC .S2 RL20,B3,0 ; |288|
STW .D2T2 B12,*+SP(60) ; |284|
|| MV .D1 A14,A8 ; |288|
|| MV .S1 A12,A4 ; |288|
|| ZERO .L2 B6 ; |288|
|| MVK .L1 0x1,A6 ; |288|
RL20: ; CALL OCCURS ; |288|
CMPLT .L1 A4,0,A0 ; |288|
[ A0] BNOP .S1 L21,4 ; |288|
[!A0] MVKL .S2 _mmZeroInit,B5 ; |289|
; BRANCH OCCURS ; |288|
;** --------------------------------------------------------------------------*
MVKH .S2 _mmZeroInit,B5 ; |289|
CALL .S2 B5 ; |289|
MVK .S2 0x10,B4 ; |289|
MVK .S1 140,A3 ; |289|
ADDKPC .S2 RL21,B3,1 ; |289|
ADD .D1X A3,SP,A4 ; |289|
RL21: ; CALL OCCURS ; |289|
MVKL .S1 _g_pEthInfo,A3 ; |292|
MVKH .S1 _g_pEthInfo,A3 ; |292|
MVKL .S1 _inet_addr,A3 ; |292|
|| LDW .D1T1 *A3,A4 ; |292|
MVKH .S1 _inet_addr,A3 ; |292|
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