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📄 tijpeg.asm

📁 用于DSP下摄像机的图像抓取、图像处理和传输、以及与上位机TCP/IP通信的工程文件。基于Texas Instruments Code Composer Studio实现。
💻 ASM
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           LDDW    .D2T1   *+SP(8),A11:A10   ; |105| 
||         MV      .S2     B13,B3            ; |105| 

           RET     .S2     B3                ; |105| 
||         LDW     .D2T2   *+SP(4),B13       ; |105| 

           LDW     .D2T1   *++SP(16),A12     ; |105| 
           NOP             4
           ; BRANCH OCCURS                   ; |105| 


;**	Parameter deleted: nHeight == s_nOutHeight;
;**	Parameter deleted: nWidth == s_nWidth;

	.sect	".text"

;******************************************************************************
;* FUNCTION NAME: _yuyv2yyyyuv                                                *
;*                                                                            *
;*   Regs Modified     : A0,A3,A4,A5,A6,A7,A8,B0,B4,B5,B6                     *
;*   Regs Used         : A0,A3,A4,A5,A6,A7,A8,B0,B3,B4,B5,B6                  *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_yuyv2yyyyuv:
;** --------------------------------------------------------------------------*
           MVKL    .S1     _s_nOutHeight,A3  ; |110| 
           MVKH    .S1     _s_nOutHeight,A3  ; |110| 
           LDW     .D1T1   *A3,A3            ; |110| 
           NOP             1
           MVKL    .S2     _s_nWidth,B5      ; |110| 
           MVKH    .S2     _s_nWidth,B5      ; |110| 
           MV      .D1X    B6,A7             ; |110| 
           CMPGT   .L1     A3,0,A0           ; |110| 
   [!A0]   B       .S1     L10               ; |110| 
           LDW     .D2T1   *B5,A8            ; |110| 
           NOP             1
           ADD     .D1     1,A3,A5           ; |115| 
           NOP             1
           SHR     .S2X    A5,1,B0           ; |115| 
           ; BRANCH OCCURS                   ; |110| 
;** --------------------------------------------------------------------------*
           CMPGT   .L1     A8,0,A0           ; |115| 
;** --------------------------------------------------------------------------*
;**   BEGIN LOOP L1
;** --------------------------------------------------------------------------*
L1:    
   [!A0]   BNOP    .S1     L5,3              ; |115| 

   [ A0]   SUB     .D1     A4,8,A4
|| [ A0]   ADD     .S1     3,A8,A3           ; |117| 

   [ A0]   SHR     .S1     A3,2,A3           ; |117| 
|| [!A0]   CMPGT   .L1     A8,0,A0           ; |129| 

           ; BRANCH OCCURS                   ; |115| 
;** --------------------------------------------------------------------------*

           SUB     .D1     A6,2,A5
||         SUB     .D2     B4,4,B5
||         SUB     .S1     A3,1,A0
||         ADD     .S2X    2,A4,B6

;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line                 : 115
;*      Loop opening brace source line   : 116
;*      Loop closing brace source line   : 127
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 36
;*      Unpartitioned Resource Bound     : 6
;*      Partitioned Resource Bound(*)    : 6
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     1        0     
;*      .D units                     6*       6*    
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             6*       6*    
;*      Long read paths              0        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          0        0     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1        0     
;*      Bound(.L .S .D .LS .LSD)     3        2     
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 36 Schedule found with 1 iterations in parallel
;*
;*      Register Usage Table:
;*          +-----------------------------------------------------------------+
;*          |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;*          |00000000001111111111222222222233|00000000001111111111222222222233|
;*          |01234567890123456789012345678901|01234567890123456789012345678901|
;*          |--------------------------------+--------------------------------|
;*       0: |*   **                          |     **                         |
;*       1: |*  ***                          |     **                         |
;*       2: |*  ***                          |     **                         |
;*       3: |*  ***                          |     **                         |
;*       4: |*  ***                          |     **                         |
;*       5: |*  ***                          |     **                         |
;*       6: |*   **                          |     **                         |
;*       7: |*   **                          |    ***                         |
;*       8: |*   **                          |    ***                         |
;*       9: |*   **                          |    ***                         |
;*      10: |*   **                          |    ***                         |
;*      11: |*   **                          |    ***                         |
;*      12: |*   **                          |     **                         |
;*      13: |*   **                          |    ***                         |
;*      14: |*   **                          |    ***                         |
;*      15: |*   **                          |    ***                         |
;*      16: |*   **                          |    ***                         |
;*      17: |*   **                          |    ***                         |
;*      18: |*   **                          |     **                         |
;*      19: |*   **                          |    ***                         |
;*      20: |*   **                          |    ***                         |
;*      21: |*   **                          |    ***                         |
;*      22: |*   **                          |    ***                         |
;*      23: |*   **                          |    ***                         |
;*      24: |*   **                          |     **                         |
;*      25: |*  ***                          |     **                         |
;*      26: |*  ***                          |     **                         |
;*      27: |*  ***                          |     **                         |
;*      28: |*  ***                          |     **                         |
;*      29: |*  ***                          |     **                         |
;*      30: |*   **                          |     **                         |
;*      31: |*  ***                          |     **                         |
;*      32: |*  ***                          |     **                         |
;*      33: |*  ***                          |     **                         |
;*      34: |*  ***                          |     **                         |
;*      35: |*  ***                          |     **                         |
;*          +-----------------------------------------------------------------+
;*
;*      Done
;*
;*      Loop is interruptible
;*      Collapsed epilog stages     : 0
;*      Collapsed prolog stages     : 0
;*
;*      Minimum safe trip count     : 1
;*----------------------------------------------------------------------------*
;*       SETUP CODE
;*
;*                  MV              A4,B6
;*                  ADD             2,B6,B6
;*
;*        SINGLE SCHEDULED ITERATION
;*
;*        C67:
;*   0              LDBU    .D1T1   *++A4(8),A3       ; |117|  ^ 
;*   1              NOP             4
;*   5              STB     .D2T1   A3,*++B5(4)       ; |117|  ^ 
;*   6              LDBU    .D2T2   *++B6(8),B4       ; |118|  ^ 
;*   7              NOP             4
;*  11              STB     .D2T2   B4,*+B5(1)        ; |118|  ^ 
;*  12              LDBU    .D2T2   *+B6(2),B4        ; |119|  ^ 
;*  13              NOP             4
;*  17              STB     .D2T2   B4,*+B5(2)        ; |119|  ^ 
;*  18              LDBU    .D1T2   *+A4(6),B4        ; |120|  ^ 
;*  19              NOP             4
;*  23              STB     .D2T2   B4,*+B5(3)        ; |120|  ^ 
;*  24              LDBU    .D1T1   *+A4(1),A3        ; |121|  ^ 
;*  25              NOP             4
;*  29              STB     .D1T1   A3,*++A5(2)       ; |121|  ^ 
;*  30              LDBU    .D1T1   *+A4(5),A3        ; |122|  ^ 
;*       || [ A0]   BDEC    .S1     C67,A0            ; |127| 
;*  31              NOP             4
;*  35              STB     .D1T1   A3,*+A5(1)        ; |122|  ^ 
;*                  ; BRANCH OCCURS                   ; |127| 
;*----------------------------------------------------------------------------*
L2:    ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L3:    ; PIPED LOOP KERNEL
           LDBU    .D1T1   *++A4(8),A3       ; |117| <0,0>  ^ 
           NOP             4
           STB     .D2T1   A3,*++B5(4)       ; |117| <0,5>  ^ 
           LDBU    .D2T2   *++B6(8),B4       ; |118| <0,6>  ^ 
           NOP             4
           STB     .D2T2   B4,*+B5(1)        ; |118| <0,11>  ^ 
           LDBU    .D2T2   *+B6(2),B4        ; |119| <0,12>  ^ 
           NOP             4
           STB     .D2T2   B4,*+B5(2)        ; |119| <0,17>  ^ 
           LDBU    .D1T2   *+A4(6),B4        ; |120| <0,18>  ^ 
           NOP             4
           STB     .D2T2   B4,*+B5(3)        ; |120| <0,23>  ^ 
           LDBU    .D1T1   *+A4(1),A3        ; |121| <0,24>  ^ 
           NOP             4
           STB     .D1T1   A3,*++A5(2)       ; |121| <0,29>  ^ 

   [ A0]   BDEC    .S1     L3,A0             ; |127| <0,30> 
||         LDBU    .D1T1   *+A4(5),A3        ; |122| <0,30>  ^ 

           NOP             4
           STB     .D1T1   A3,*+A5(1)        ; |122| <0,35>  ^ 
;** --------------------------------------------------------------------------*
L4:    ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*

           ADD     .D1     2,A5,A6
||         ADD     .S1     8,A4,A4
||         ADD     .D2     4,B5,B4

           CMPGT   .L1     A8,0,A0           ; |129| 
;** --------------------------------------------------------------------------*
L5:    
   [!A0]   BNOP    .S1     L9,2              ; |129| 

   [ A0]   SUB     .D1     A4,8,A4
|| [ A0]   ADD     .S1     3,A8,A3           ; |131| 
|| [!A0]   SUB     .D2     B0,1,B0           ; |142| 

   [ A0]   SHR     .S1     A3,2,A3           ; |131| 

   [ A0]   SUB     .D1     A7,2,A5
|| [ A0]   SUB     .D2     B4,4,B5
|| [ A0]   SUB     .S1     A3,1,A0
|| [ A0]   ADD     .S2X    2,A4,B6

           ; BRANCH OCCURS                   ; |129| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line                 : 129
;*      Loop opening brace source line   : 130
;*      Loop closing brace source line   : 141
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 36
;*      Unpartitioned Resource Bound     : 6
;*      Partitioned Resource Bound(*)    : 6
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     1        0     
;*      .D units                     6*       6*    
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             6*       6*    
;*      Long read paths              0        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          0        0     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1        0     
;*      Bound(.L .S .D .LS .LSD)     3        2     
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 36 Schedule found with 1 iterations in parallel
;*
;*      Register Usage Table:
;*          +-----------------------------------------------------------------+
;*          |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;*          |00000000001111111111222222222233|00000000001111111111222222222233|
;*          |01234567890123456789012345678901|01234567890123456789012345678901|
;*          |--------------------------------+--------------------------------|
;*       0: |*   **                          |     **                         |
;*       1: |*  ***                          |     **                         |
;*       2: |*  ***                          |     **                         |
;*       3: |*  ***                          |     **                         |
;*       4: |*  ***                          |     **                         |
;*       5: |*  ***                          |     **                         |
;*       6: |*   **                          |     **                         |
;*       7: |*   **                          |    ***                         |
;*       8: |*   **                          |    ***                         |
;*       9: |*   **                          |    ***                         |
;*      10: |*   **                          |    ***                         |
;*      11: |*   **                          |    ***                         |
;*      12: |*   **                          |     **                         |
;*      13: |*   **                          |    ***                         |
;*      14: |*   **                          |    ***                         |
;*      15: |*   **                          |    ***                         |
;*      16: |*   **                          |    ***                         |
;*      17: |*   **                          |    ***                         |
;*      18: |*   **                          |     **                         |
;*      19: |*   **                          |    ***                         |
;*      20: |*   **                          |    ***                         |
;*      21: |*   **                          |    ***                         |
;*      22: |*   **                          |    ***                         |
;*      23: |*   **                          |    ***                         |
;*      24: |*   **                          |     **                         |
;*      25: |*  ***                          |     **                         |
;*      26: |*  ***                          |     **                         |
;*      27: |*  ***                          |     **                         |
;*      28: |*  ***                          |     **                         |
;*      29: |*  ***                          |     **                         |
;*      30: |*   **                          |     **                         |
;*      31: |*  ***                          |     **                         |
;*      32: |*  ***                          |     **                         |
;*      33: |*  ***                          |     **                         |
;*      34: |*  ***                          |     **                         |
;*      35: |*  ***                          |     **                         |
;*          +-----------------------------------------------------------------+
;*
;*      Done
;*
;*      Loop is interruptible
;*      Collapsed epilog stages     : 0
;*      Collapsed prolog stages     : 0
;*
;*      Minimum safe trip count     : 1
;*----------------------------------------------------------------------------*
;*       SETUP CODE
;*
;*                  MV              A4,B6
;*                  ADD             2,B6,B6
;*
;*        SINGLE SCHEDULED ITERATION
;*
;*        C30:
;*   0              LDBU    .D1T1   *++A4(8),A3       ; |131|  ^ 
;*   1              NOP             4
;*   5              STB     .D2T1   A3,*++B5(4)       ; |131|  ^ 

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