📄 protocal.asm
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MVKH .S2 _g_nMakeCfgStatus,B5 ; |123|
[ A0] LDW .D2T2 *B5,B0 ; |123|
|| ZERO .S2 B0 ; |124|
[ A0] MVKL .S1 _g_cfgIPHeader+20,A3 ; |124|
[ A0] MVKL .S2 0xcf03,B4 ; |124|
[ A0] MVKH .S1 _g_cfgIPHeader+20,A3 ; |124|
[ A0] MVKH .S2 0xcf03,B4 ; |124|
[ B0] STH .D1T2 B4,*A3 ; |124|
MVKL .S2 _LinkCheckSum__6CiLinkFPUsi,B6 ; |127|
MVKH .S2 _LinkCheckSum__6CiLinkFPUsi,B6 ; |127|
;** --------------------------------------------------------------------------*
L13:
CALL .S2 B6 ; |127|
MVKL .S1 _g_cfgIPHeader+26,A3 ; |126|
MVKL .S2 _g_cfgIPHeader,B5 ; |127|
MVKH .S1 _g_cfgIPHeader+26,A3 ; |126|
MVKH .S2 _g_cfgIPHeader,B5 ; |127|
|| ZERO .D1 A5 ; |126|
ADDKPC .S2 RL3,B3,0 ; |127|
|| STH .D1T1 A5,*A3 ; |126|
|| MV .D2 B5,B4 ; |127|
|| MVK .S1 0x1c,A6 ; |127|
RL3: ; CALL OCCURS ; |127|
LDW .D1T1 *+A7(4),A3 ; |128|
MVKL .S2 _g_cfgIPHeader+26,B4 ; |127|
MVKH .S2 _g_cfgIPHeader+26,B4 ; |127|
MV .D2X A4,B6 ; |127|
STH .D2T2 B6,*B4 ; |127|
LDW .D1T1 *+A3(20),A3 ; |128|
NOP 1
LDW .D1T1 *+A7(4),A4 ; |128|
LDW .D2T2 *++SP(8),B3 ; |130|
MV .D2 B5,B4 ; |127|
LDH .D1T1 *+A3(16),A5 ; |128|
LDW .D1T1 *+A3(20),A3 ; |128|
NOP 4
CALLRET .S2X A3 ; |128|
NOP 4
ADD .D1 A5,A4,A4 ; |128|
RL4: ; CALL OCCURS ; |130| ; bypass _LinkIPReply__6CiLinkFv upon return
.sect ".text"
.global _LinkIPParse__6CiLinkFv
;******************************************************************************
;* FUNCTION NAME: CiLink::_LinkIPParse() *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14, *
;* A15,B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12, *
;* B13,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24,A25, *
;* A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20,B21, *
;* B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14, *
;* A15,B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12, *
;* B13,DP,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Local Frame Size : 0 Args + 28 Auto + 44 Save = 72 byte *
;******************************************************************************
_LinkIPParse__6CiLinkFv:
;** --------------------------------------------------------------------------*
MVKL .S1 _g_nNeedReply,A3 ; |179|
MVKH .S1 _g_nNeedReply,A3 ; |179|
LDW .D1T1 *A3,A5 ; |179|
MVKL .S2 _TSK_timerSem,B6 ; |182|
MVKL .S2 _SEM_pend,B5 ; |182|
MVK .S2 0x1388,B4 ; |182|
MV .D1X SP,A31 ; |171|
CMPEQ .L1 A5,1,A0 ; |179|
[!A0] B .S1 L14 ; |179|
STW .D2T1 A15,*SP--(72) ; |171|
STDW .D1T1 A11:A10,*-A31(40)
|| MVKH .S2 _TSK_timerSem,B6 ; |182|
STDW .D1T1 A13:A12,*-A31(32)
|| STDW .D2T2 B13:B12,*+SP(64)
|| MVKH .S2 _SEM_pend,B5 ; |182|
STW .D1T1 A14,*-A31(24)
|| MVKL .S1 _g_nNeedReply,A3 ; |181|
|| MVKL .S2 _LinkIPReply__6CiLinkFv,B10 ; |183|
|| STDW .D2T2 B11:B10,*+SP(56)
|| MV .L1 A4,A11 ; |171|
ZERO .D1 A5 ; |181|
|| STW .D2T2 B3,*+SP(52)
|| MV .L1X B6,A4 ; |182|
|| MVKH .S2 _LinkIPReply__6CiLinkFv,B10 ; |183|
|| MVKH .S1 _g_nNeedReply,A3 ; |181|
; BRANCH OCCURS ; |179|
;** --------------------------------------------------------------------------*
CALL .S2 B5 ; |182|
ADDKPC .S2 RL5,B3,1 ; |182|
STW .D1T1 A5,*A3 ; |181|
NOP 2
RL5: ; CALL OCCURS ; |182|
CALL .S2 B10 ; |183|
MV .D1 A11,A4 ; |183|
ADDKPC .S2 RL6,B3,3 ; |183|
RL6: ; CALL OCCURS ; |183|
;** --------------------------------------------------------------------------*
L14:
LDW .D1T1 *+A11(4),A3 ; |186|
LDW .D1T1 *+A11(4),A4 ; |186|
LDW .D1T2 *+A11(12),B4 ; |186|
ZERO .D2 B6 ; |186|
MVK .S1 0x80,A6 ; |186|
LDW .D1T1 *+A3(20),A3 ; |186|
NOP 4
LDH .D1T1 *+A3(24),A5 ; |186|
LDW .D1T1 *+A3(28),A3 ; |186|
NOP 4
CALL .S2X A3 ; |186|
ADD .D1 A5,A4,A4 ; |186|
ADDKPC .S2 RL7,B3,3 ; |186|
RL7: ; CALL OCCURS ; |186|
MV .D1 A4,A0 ; |186|
[ A0] B .S1 L22 ; |186|
MVKL .S2 _LinkCheckSum__6CiLinkFPUsi,B5 ; |193|
MV .L1 A11,A4 ; |193|
|| MVK .S1 0x1c,A6 ; |193|
|| MVKH .S2 _LinkCheckSum__6CiLinkFPUsi,B5 ; |193|
|| [!A0] LDW .D1T1 *+A11(12),A3 ; |192|
|| [ A0] LDW .D2T2 *+SP(52),B3 ; |266|
NOP 1
[ A0] MV .D1X SP,A31 ; |266|
[ A0] LDDW .D1T1 *+A31(40),A13:A12 ; |266|
; BRANCH OCCURS ; |186|
;** --------------------------------------------------------------------------*
LDW .D1T1 *+A11(12),A5 ; |192|
LDW .D1T1 *A3,A3 ; |192|
NOP 2
CALL .S2 B5 ; |193|
ADDKPC .S2 RL8,B3,0 ; |193|
AND .D1 15,A3,A3 ; |192|
ADDAW .D1 A5,A3,A7 ; |192|
NOP 1
MV .D2X A7,B4 ; |193|
RL8: ; CALL OCCURS ; |193|
MV .D1 A4,A0 ; |193|
[ A0] B .S1 L21 ; |193|
MVK .S2 99,B5
MVKL .S2 _g_pEthInfo,B4
|| ADD .D2 SP,16,B6
ADD .S1X 4,SP,A3 ; |195|
|| MVKH .S2 _g_pEthInfo,B4
|| MVK .D2 0x6,B6 ; |198|
|| SUB .L2 B6,1,B9 ; |202|
|| [!A0] LDNDW .D1T1 *A7,A9:A8 ; |195|
[!A0] LDNDW .D1T1 *+A7(8),A5:A4 ; |195|
[!A0] LDNW .D1T1 *+A7(24),A16 ; |195|
; BRANCH OCCURS ; |193|
;** --------------------------------------------------------------------------*
LDNDW .D1T1 *+A7(16),A7:A6 ; |195|
NOP 1
STNDW .D1T1 A9:A8,*A3 ; |195|
STNDW .D1T1 A5:A4,*+A3(8) ; |195|
STNW .D1T1 A16,*+A3(24) ; |195|
STNDW .D1T1 A7:A6,*+A3(16) ; |195|
LDW .D2T2 *B4,B4
NOP 2
LDBU .D2T2 *++B9,B7 ; |200| (P) <0,1> ^
NOP 1
ADD .S2 B5,B4,B4
LDBU .D2T2 *++B4,B8 ; |200| (P) <0,0> ^
NOP 1
MVC .S2 CSR,B17
MVK .D1 0x1,A0
|| AND .D2 -2,B17,B16
MV .D1 A0,A1
|| MVC .S2 B16,CSR ; interrupts off
|| ZERO .D2 B5
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 198
;* Loop opening brace source line : 199
;* Loop closing brace source line : 202
;* Known Minimum Trip Count : 1
;* Known Maximum Trip Count : 6
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 10
;* Unpartitioned Resource Bound : 3
;* Partitioned Resource Bound(*) : 3
;* Resource Partition:
;* A-side B-side
;* .L units 0 1
;* .S units 1 0
;* .D units 0 2
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 0 2
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 4 5 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2 3*
;*
;* Searching for software pipeline schedule at ...
;* ii = 10 Did not find schedule
;* ii = 11 Schedule found with 2 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |** | ****** |
;* 1: |** | ****** * |
;* 2: |** | ****** * |
;* 3: |** | ****** * |
;* 4: |* |* ****** |
;* 5: |* | ****** |
;* 6: |* | ****** |
;* 7: |* | ****** |
;* 8: |* | ****** |
;* 9: |* * | ****** |
;* 10: |* * | ****** |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Collapsed epilog stages : 1
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* For further improvement on this loop, try option -mh14
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,A0
;* ZERO B5
;* ZERO B7
;* ZERO B8
;* MV A0,A1
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C267:
;* 0 [ A0] LDBU .D2T2 *++B4,B8 ; |200| ^
;* 1 [ A0] LDBU .D2T2 *++B9,B7 ; |200| ^
;* 2 NOP 4
;* 6 CMPEQ .L2 B7,B8,B16 ; |200| ^
;* 7 XOR .D2 1,B16,B16 ; |200| ^
;* 8 SUB .S2 B16,1,B16 ; |200| ^
;* || SUB .D2 B6,1,B6 ; |202|
;* 9 AND .S2 B16,B6,B0 ; |202| ^
;* || [ A1] MV .D2 B16,B5 ; |202|
;* 10 [!B0] ZERO .D1 A0 ; ^
;* 11 [ A0] B .S1 C267 ; |202|
;* 12 NOP 2
;* 14 MV .D1 A0,A3 ; Split a long life
;* 15 NOP 1
;* 16 MV .D1 A3,A1 ; Split a long life
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