boot.lst

cypress cy3721做的外部无线结点。感知温度后将温度值反给中心结点。

   529                              or    reg[@0], @1               ; enable specified interrupt enable bit
   530  1C5C                        endm
   531                          
   532                          ;----------------------------------------------------
   533                          ;  Clear Posted Interrupt Flag Mask
   534                          ;
   535                          ;  Use the following macros to clear the
   536                          ;  bits in the Interrupt Clear registers,
   537                          ;  INT_CLR0, INT_CLR1 or INT_CLR3.
   538                          ;  Usage:    M8C_ClearIntFlag INT_CLRN, MASK
   539                          ;
   540                          ;  where INT_MSKN is INT_CLR0, INT_CLR1 or INT_CLR3
   541                          ;        and MASK is the bit set to enable or disable
   542                          ;----------------------------------------------------
   543                              macro M8C_ClearIntFlag
   544                              mov   reg[@0], ~@1              ; clear specified interrupt enable bit
   545  1C5C                        endm
   546                          
   547                          ;----------------------------------------------------
   548                          ;  Power-On Reset & WatchDog Timer Functions
   549                          ;----------------------------------------------------
   550                              macro M8C_EnableWatchDog
   551                              and   reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
   552  1C5C                        endm
   553                          
   554                              macro M8C_ClearWDT
   555                              mov   reg[RES_WDT], 00h
   556  1C5C                        endm
   557                          
   558                              macro M8C_ClearWDTAndSleep
   559                              mov   reg[RES_WDT], 38h
   560  1C5C                        endm
   561                          
   562                          ;----------------------------------------------------
   563                          ;  Sleep, CPU Stop & Software Reset
   564                          ;----------------------------------------------------
   565                              macro M8C_Sleep
   566                              or    reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
   567                              ; The next instruction to be executed depends on the state of the
   568                              ; various interrupt enable bits. If some interrupts are enabled
   569                              ; and the global interrupts are disabled, the next instruction will
   570                              ; be the one that follows the invocation of this macro. If global
   571                              ; interrupts are also enabled then the next instruction will be
   572                              ; from the interrupt vector table. If no interrupts are enabled
   573                              ; then the CPU sleeps forever.
   574  1C5C                        endm
   575                          
   576                              macro M8C_Stop
   577                              ; In general, you probably don't want to do this, but here's how:
   578                              or    reg[CPU_SCR0], CPU_SCR0_STOP_MASK
   579                              ; Next instruction to be executed is located in the interrupt
   580                              ; vector table entry for Power-On Reset.
   581  1C5C                        endm
   582                          
   583                              macro M8C_Reset
   584                              ; Restore CPU to the power-on reset state.
   585                              mov A, 0
   586                              SSC
   587                              ; Next non-supervisor instruction will be at interrupt vector 0.
   588  1C5C                        endm
   589                          
   590                          ;----------------------------------------------------
   591                          ; ImageCraft Code Compressor Actions
   592                          ;----------------------------------------------------
   593                              ; Suspend Code Compressor
   594                              ; Must not span a RET or RETI instruction
   595                              ; without resuming code compression
   596                              macro Suspend_CodeCompressor
   597                              or   F, 0
   598  1C5C                        endm
   599                          
   600                              ; Resume Code Compression
   601                              macro Resume_CodeCompressor
   602                              add  SP, 0
   603  1C5C                        endm
     1                          ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
     2                          ;;;
     3                          ;;;  M8SSC.INC -- M8C21x3x Microcontroller Device SSC Declarations
     4                          ;;;
     5                          ;;;  Copyright (c) 2004, Cypress MicroSystems, Inc. All rights reserved.
     6                          ;;;
     7                          ;;;
     8                          ;;;  This file provides address constants, bit field masks and a set of macro
     9                          ;;;  facilities for the Cypress MicroSystems 21x3x Microcontroller family.
    10                          ;;;
    11                          ;;;  Last Modified: August 17, 2004
    12                          ;;;
    13                          ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    14                          
    15                          ;----------------------------------
    16                          ; Common Supervisory Code Variables
    17                          ;----------------------------------
    18  00F8                    bSSC_KEY1:                          equ      0F8h   ; supervisory key
    19  00F9                    bSSC_KEYSP:                         equ      0F9h   ; supervisory stack ptr key
    20  00FA                    bSSC_TABLE_TableId:                 equ      0FAh   ; table ID
    21                          
    22  003A                    OPER_KEY:                           equ      3Ah   ; operation key
    23                          
    24                          ;----------------------------------
    25                          ; SSC_Action macro command codes
    26                          ;----------------------------------
    27  0001                    FLASH_READ:                         equ      1     ; flash read command
    28  0002                    FLASH_WRITE:                        equ      2     ; flash write command
    29  0003                    FLASH_ERASE:                        equ      3     ; flash erase command
    30  0004                    PROTECT_BLOCK:                      equ      4     ; flash protect block command
    31  0006                    TABLE_READ:                         equ      6     ; table read command
    32  0007                    FLASH_CHECKSUM:                     equ      7     ; flash checksum calculation command
    33  0008                    CALIBRATE0:                         equ      8     ; Calibrate without checksum
    34  0009                    CALIBRATE1:                         equ      9     ; Calibrate with checksum
    35                          
    36                          ;----------------------------------
    37                          ; SSC_Action Flash table addresses
    38                          ;----------------------------------
    39                          ; Table 0 Values
    40  00F8                    SILICON_ID_1:                       equ      0F8h   ; Table 0 first byte of silicon ID
    41  00F9                    SILICON_ID_0:                       equ      0F9h   ; Table 0 second byte of silicon ID
    42                          
    43                          ; Table 1 Values
    44  00F8                    SSCTBL1_TRIM_BGR_3V:                equ      0F8h   ; 3.3V bandgap ref voltage trim
    45  00F9                    SSCTBL1_TRIM_IMO_3V_24MHZ:          equ      0F9h   ; 3.3V internal main oscillator trim (24MHz)
    46  00FA                    SSCTBL1_CAL_ROOM_3V:                equ      0FAh   ; 3.3V Room Temp Calibration
    47  00FB                    SSCTBL1_CAL_HOT_3V:                 equ      0FBh   ; 3.3V Hot  Temp Calibration
    48  00FC                    SSCTBL1_TRIM_BGR_5V:                equ      0FCh   ; 5.0V bandgap ref voltage trim
    49  00FD                    SSCTBL1_TRIM_IMO_5V_24MHZ:          equ      0FDh   ; 5.0V internal main oscillator trim (24MHz)
    50  00FE                    SSCTBL1_CAL_ROOM_5V:                equ      0FEh   ; 5.0V Room Temp Calibration
    51  00FF                    SSCTBL1_CAL_HOT_5V:                 equ      0FFh   ; 5.0V Hot  Temp Calibration
    52                              ; legacy names:
    53  00F8                        VOLTAGE_TRIM_3V:                equ      0F8h   ; Table 1 3.3V bandgap ref voltage trim value
    54  00F9                        OSCILLATOR_TRIM_3V:             equ      0F9h   ; Table 1 3.3V internal main oscillator trim val
                                ue
    55  00FC                        VOLTAGE_TRIM_5V:                equ      0FCh   ; Table 1 5.0V bandgap ref voltage trim value
    56  00FD                        OSCILLATOR_TRIM_5V:             equ      0FDh   ; Table 1 5.0V internal main oscillator trim val
                                ue
    57                          
    58                          ; Table 2 Values
    59  00F8                    SSCTBL2_TRIM_BGR_2V:                equ      0F8h   ; 2.7V bandgap ref voltage trim
    60  00F9                    SSCTBL2_TRIM_IMO_2V_12MHZ:          equ      0F9h   ; 2.7V internal main oscillator trim (12MHz)
    61  00FA                    SSCTBL2_CAL_ROOM_2V:                equ      0FAh   ; 2.7V Room Temp Calibration
    62  00FB                    SSCTBL2_CAL_HOT_2V:                 equ      0FBh   ; 2.7V Hot  Temp Calibration
    63  00FC                    SSCTBL2_TRIM_IMO_3V_6MHZ:           equ      0FCh   ; 3.3V IMO Trim for SLOWIMO 6MHz operation
    64  00FD                    SSCTBL2_TRIM_IMO_2V_6MHZ:           equ      0FDh   ; 2.7V IMO Trim for SLOWIMO 6MHz operation
    65  00FE                    SSCTBL2_TRIM_IMO_5V_6MHZ:           equ      0FEh   ; 5.0V IMO Trim for SLOWIMO 6MHz operation
    66                          
    67                          
    68                          ;-----------------------------------------------------------------------------
    69                          ;  MACRO SSC_Action( OpCode )
    70                          ;
    71                          ;  DESCRIPTION:
    72                          ;     Performs supervisory operations defined in Supervisory ROM (SROM)
    73                          ;     section of Technical Reference Manual and/or Datasheet.
    74                          ;-----------------------------------------------------------------------------
    75                          ;
    76                          ;  ARGUMENTS:
    77                          ;     BYTE  OpCode   - specified supervisory operation - defined operations
    78                          ;