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HI-TECH Software Macro Assembler (PSoC MCU) V9.61PL1
Fri Oct 03 08:10:16 2008
1 ; Generated by PSoC Designer ???
2 ;
3 ;=============================================================================
4 ; FILENAME: GlobalParams.inc
5 ; DATE: 27 September 2004
6 ;
7 ; DESCRIPTION:
8 ; Constants describing many of the global parameter settings.
9 ; This file contains equates to support oscillator register initialization
10 ; for the CY8C21434MLF
11 ;
12 ; Copyright (C) Cypress MicroSystems 2000-2004. All rights reserved.
13 ;
14 ; NOTES:
15 ; Do not modify this file. It is generated by PSoC Designer each time the
16 ; generate application function is run. The values of the parameters in this
17 ; file can be modified by changing the values of the global parameters in the
18 ; device editor.
19 ;=============================================================================
20 ;
21
22 0002 CPU_CLOCK: equ 2h ;CPU clock value
23 0007 CPU_CLOCK_MASK: equ 7h ;CPU clock mask
24 0002 CPU_CLOCK_JUST: equ 2h ;CPU clock value justified
25 0000 SLEEP_TIMER: equ 0h ;Sleep Timer value
26 0018 SLEEP_TIMER_MASK: equ 18h ;Sleep Timer mask
27 0000 SLEEP_TIMER_JUST: equ 0h ;Sleep Timer value justified
28 0001 SWITCH_MODE_PUMP: equ 1h ;Switch Mode Pump setting
29 0080 SWITCH_MODE_PUMP_MASK: equ 80h ;Switch Mode Pump mask
30 0080 SWITCH_MODE_PUMP_JUST: equ 80h ;Switch Mode Pump justified
31 0000 LVD_TBEN: equ 0 ; Low Voltage Throttle-back enable value
32 0008 LVD_TBEN_MASK: equ 8 ; Low Voltage Throttle-back enable mask
33 0000 LVD_TBEN_JUST: equ 0 ; Low Voltage Throttle-back enable justified
34 0003 TRIP_VOLTAGE: equ 3h ;Trip Voltage value
35 0007 TRIP_VOLTAGE_MASK: equ 7h ;Trip Voltage mask
36 0003 TRIP_VOLTAGE_JUST: equ 3h ;Trip Voltage justified
37
38 0008 POWER_SETTING: equ 8h
39 0010 POWER_SET_5V0: equ 10h ; MASK for 5.0V operation, fast and slow
40 0010 POWER_SET_5V0_24MHZ: equ 10h ; Power Setting value for 5.0V fast
41 0011 POWER_SET_5V0_6MHZ: equ 11h ; Power Setting value for 5.0V slow
42 0008 POWER_SET_3V3: equ 08h ; MASK for 3.3V operation, fast and slow
43 0008 POWER_SET_3V3_24MHZ: equ 08h ; Power Setting value for 3.3V fast
44 0009 POWER_SET_3V3_6MHZ: equ 09h ; Power Setting value for 3.3V slow
45 0006 POWER_SET_2V7: equ 06h ; MASK for 2.7V operation, fast and slow
46 0004 POWER_SET_2V7_12MHZ: equ 04h ; MASK for 2.7V, 12MHZ operation
47 0002 POWER_SET_2V7_6MHZ: equ 02h ; MASK for 2.7V, 6MHZ operation
48 0001 POWER_SET_SLOW_IMO: equ 01h ; MASK for slow Internal Main Oscillator (IMO)
49
50 0000 COMM_RX_PRESENT: equ 0 ;1 = TRUE
51 0000 WATCHDOG_ENABLE: equ 0 ;Watchdog Enable 1 = Enable
52
53 000B CLOCK_DIV_VC1: equ bh ;VC1 clock divider
54 00F0 CLOCK_DIV_VC1_MASK: equ f0h ;VC1 clock divider mask
55 00B0 CLOCK_DIV_VC1_JUST: equ b0h ;VC1 clock divider justified
56 0007 CLOCK_DIV_VC2: equ 7h ;VC2 clock divider
57 000F CLOCK_DIV_VC2_MASK: equ fh ;VC2 clock divider mask
58 0007 CLOCK_DIV_VC2_JUST: equ 7h ;VC2 clock divider justified
59 0001 CLOCK_INPUT_VC3: equ 1h ;VC3 clock source
60 0003 CLOCK_INPUT_VC3_MASK: equ 3h ;VC3 clock source mask
61 0001 CLOCK_INPUT_VC3_JUST: equ 1h ;VC3 clock source justified
62 007F CLOCK_DIV_VC3: equ 7fh ;VC3 clock divider
63 00FF CLOCK_DIV_VC3_MASK: equ ffh ;VC3 clock divider mask
64 007F CLOCK_DIV_VC3_JUST: equ 7fh ;VC3 clock divider justified
65 0000 SYSCLK_SOURCE: equ (0h | 0h) ;SysClk Source setting
66 0006 SYSCLK_SOURCE_MASK: equ (4h | 2h) ;SysClk Source setting mask
67 0000 SYSCLK_SOURCE_JUST: equ (0h | 0h) ;SysClk Source setting justified
68 0000 SYSCLK_2_DISABLE: equ 0h ;SysClk*2 Disable setting
69 0001 SYSCLK_2_DISABLE_MASK: equ 1h ;SysClk*2 Disable setting mask
70 0000 SYSCLK_2_DISABLE_JUST: equ 0h ;SysClk*2 Disable setting justified
71 ;
72 ; register initial values
73 ;
74 0000 ANALOG_IO_CONTROL: equ 0h ;Analog IO Control register (ABF_CR)
75 0000 PORT_0_GLOBAL_SELECT: equ 0h ;Port 0 global select register (PRT0GS)
76 0000 PORT_0_DRIVE_0: equ 0h ;Port 0 drive mode 0 register (PRT0DM0)
77 00FF PORT_0_DRIVE_1: equ ffh ;Port 0 drive mode 1 register (PRT0DM1)
78 00FF PORT_0_DRIVE_2: equ ffh ;Port 0 drive mode 2 register (PRT0DM2)
79 0000 PORT_0_INTENABLE: equ 0h ;Port 0 interrupt enable register (PRT0IE)
80 0000 PORT_0_INTCTRL_0: equ 0h ;Port 0 interrupt control 0 register (PRT0IC0)
81 0000 PORT_0_INTCTRL_1: equ 0h ;Port 0 interrupt control 1 register (PRT0IC1)
82 0040 PORT_1_GLOBAL_SELECT: equ 40h ;Port 1 global select register (PRT1GS)
83 00E0 PORT_1_DRIVE_0: equ e0h ;Port 1 drive mode 0 register (PRT1DM0)
84 00BF PORT_1_DRIVE_1: equ bfh ;Port 1 drive mode 1 register (PRT1DM1)
85 00BF PORT_1_DRIVE_2: equ bfh ;Port 1 drive mode 2 register (PRT1DM2)
86 0000 PORT_1_INTENABLE: equ 0h ;Port 1 interrupt enable register (PRT1IE)
87 0000 PORT_1_INTCTRL_0: equ 0h ;Port 1 interrupt control 0 register (PRT1IC0)
88 0000 PORT_1_INTCTRL_1: equ 0h ;Port 1 interrupt control 1 register (PRT1IC1)
89 0000 PORT_2_GLOBAL_SELECT: equ 0h ;Port 2 global select register (PRT2GS)
90 0000 PORT_2_DRIVE_0: equ 0h ;Port 2 drive mode 0 register (PRT2DM0)
91 00FF PORT_2_DRIVE_1: equ ffh ;Port 2 drive mode 1 register (PRT2DM1)
92 00FF PORT_2_DRIVE_2: equ ffh ;Port 2 drive mode 2 register (PRT2DM2)
93 0000 PORT_2_INTENABLE: equ 0h ;Port 2 interrupt enable register (PRT2IE)
94 0000 PORT_2_INTCTRL_0: equ 0h ;Port 2 interrupt control 0 register (PRT2IC0)
95 0000 PORT_2_INTCTRL_1: equ 0h ;Port 2 interrupt control 1 register (PRT2IC1)
96 0000 PORT_3_GLOBAL_SELECT: equ 0h ;Port 3 global select register (PRT3GS)
97 0000 PORT_3_DRIVE_0: equ 0h ;Port 3 drive mode 0 register (PRT3DM0)
98 000F PORT_3_DRIVE_1: equ fh ;Port 3 drive mode 1 register (PRT3DM1)
99 000F PORT_3_DRIVE_2: equ fh ;Port 3 drive mode 2 register (PRT3DM2)
100 0000 PORT_3_INTENABLE: equ 0h ;Port 3 interrupt enable register (PRT3IE)
101 0000 PORT_3_INTCTRL_0: equ 0h ;Port 3 interrupt control 0 register (PRT3IC0)
102 0000 PORT_3_INTCTRL_1: equ 0h ;Port 3 interrupt control 1 register (PRT3IC1)
1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ;;;
3 ;;; M8C.INC -- M8C21030 Microcontroller Device System Declarations
4 ;;;
5 ;;; Copyright (c) 2005 Cypress MicroSystems, Inc. All rights reserved.
6 ;;;
7 ;;;
8 ;;; This file provides address constants, bit field masks and a set of macro
9 ;;; facilities for the Cypress MicroSystems 21x3x Microcontroller devices.
10 ;;;
11 ;;; Last Modified: January 21, 2005
12 ;;;
13 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14
15 ;;=============================================================================
16 ;; Definition of abbreviations used in the descriptions below
17 ;; (RW) The register or bit supports reads and writes
18 ;; (W) The register or bit is write-only
19 ;; (R) The register or bit is read-only
20 ;; (#) Access to the register is bit specific (see the family datasheet)
21 ;; (RC) The register or bit can be read, but writing a 0 will clear it,
22 ;; writing a 1 will have no effect.
23 ;;=============================================================================
24
25 ;;=============================================================================
26 ;; System Registers
27 ;;=============================================================================
28
29 ;----------------------------
30 ; Flag Register Bit Fields
31 ;----------------------------
32 00C0 FLAG_PGMODE_MASK: equ 0C0h ; Paging control for > 256 bytes of RAM
33 0000 FLAG_PGMODE_0: equ 00h ; Direct to Page 0, indexed to Page 0
34 0040 FLAG_PGMODE_1: equ 40h ; Direct to Page 0, indexed to STK_PP page
35 0080 FLAG_PGMODE_2: equ 80h ; Direct to CUR_PP page, indexed to IDX_PP page
36 00C0 FLAG_PGMODE_3: equ 0C0h ; Direct to CUR_PP page, indexed to STK_PP page
37 0000 FLAG_PGMODE_00b: equ 00h ; Same as PGMODE_0
38 0040 FLAG_PGMODE_01b: equ 40h ; Same as PGMODE_1
39 0080 FLAG_PGMODE_10b: equ 80h ; Same as PGMODE_2
40 00C0 FLAG_PGMODE_11b: equ 0C0h ; Same as PGMODE_3
41 0010 FLAG_XIO_MASK: equ 10h ; I/O Bank select for register space
42 0008 FLAG_SUPER: equ 08h ; Supervisor Mode
43 0004 FLAG_CARRY: equ 04h ; Carry Condition Flag
44 0002 FLAG_ZERO: equ 02h ; Zero Condition Flag
45 0001 FLAG_GLOBAL_IE: equ 01h ; Glogal Interrupt Enable
46
47
48 ;;=============================================================================
49 ;; Register Space, Bank 0
50 ;;=============================================================================
51
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