ezi2cs.inc

cypress cy3721做的外部无线结点。感知温度后将温度值反给中心结点。

;;*****************************************************************************
;;*****************************************************************************
;;  FILENAME: EzI2Cs.inc
;;  Version: 1.1, Updated on 2008/10/2 at 14:38:50
;;  Generated by PSoC Designer ???
;;
;;  DESCRIPTION: Assembler declarations for the EzI2Cs user module for the 
;;               29/27/24/22xxx PSoC family of devices
;;-----------------------------------------------------------------------------
;;  Copyright (c) Cypress MicroSystems 2004. All Rights Reserved.
;;*****************************************************************************
;;*****************************************************************************


;--------------------------------------------------
; Constants for EzI2Cs API's.
;--------------------------------------------------
EzI2Cs_DYNAMIC_ADDR:                   equ   1
EzI2Cs_ROM_ENABLE:                     equ   1
EzI2Cs_SYNC_FIX:                       equ   0

IF (EzI2Cs_ROM_ENABLE) 
   EzI2Cs_ADDR_MASK:                        equ  0x7E    ; Mask off ROM Addr and R/W bit
ELSE
   EzI2Cs_ADDR_MASK:                        equ  0xFE    ; Mask off  R/W bit
ENDIF

;; I2C_CFG Register definitions
EzI2Cs_CFG_PSelect:                         equ  0x40   ; Pin Select, 0 = P1,7/5, 1 = P1,1,0
EzI2Cs_CFG_BUS_ERROR_IE:                    equ  0x20   ; Enable Interrupt on bus error
EzI2Cs_CFG_STOP_IE:                         equ  0x10   ; Enable Interrupt on Stop condition
EzI2Cs_CFG_CLOCK_100K:                      equ  0x00   ; 100kHz Standard clock rate
EzI2Cs_CFG_CLOCK_400K:                      equ  0x04   ; 400kHz Fast Mode
EzI2Cs_CFG_CLOCK_50K:                       equ  0x08   ; 50kHz  Standard Mode
EzI2Cs_CFG_Master_EN:                       equ  0x02   ; Enable Master Mode.               
EzI2Cs_CFG_Slave_EN:                        equ  0x01   ; Enable Slave Mode.               

;; I2C_SCR Register definitions
EzI2Cs_SCR_BUS_ERROR:                       equ  0x80  ; Bus Error                    
EzI2Cs_SCR_LOST_ARB:                        equ  0x40  ; Lost Arbitration  (Master Only)
EzI2Cs_SCR_STOP_STATUS:                     equ  0x20  ; Stop Status                  
EzI2Cs_SCR_ACK:                             equ  0x10  ; ACK Status                   
EzI2Cs_SCR_NAK:                             equ  0x00  ; NAK Status                   
EzI2Cs_SCR_ADDRESS:                         equ  0x08  ; Data is address.
EzI2Cs_SCR_TRANSMIT:                        equ  0x04  ; Sets direction of data flow                
EzI2Cs_SCR_LRB:                             equ  0x02  ; Last Received Bit                
EzI2Cs_SCR_BYTE_COM:                        equ  0x01  ; Byte Complete   

;; I2C_DR  Register definitions (Data Register)

;; I2C_MSCR Register definitions  (Master Mode Only)
EzI2Cs_MSCR_BUS_BUSY:                       equ  0x08  ; Bus is Busy with other trafic        
EzI2Cs_MSCR_MASTER_MODE:                    equ  0x04  ; ?????
EzI2Cs_MSCR_RESTART_REN:                    equ  0x02  ; Generate a Restart
EzI2Cs_MSCR_START_REN:                      equ  0x01  ; Generate a Start


;; Valid address
EzI2Cs_SLAVE_ADDR:                          equ  (0x4<<1)        ; Permanent Slave Address
EzI2Cs_ALT_SLAVE_ADDR:                      equ  ((0x4<<1)&0x80) ; Permanent Slave Address

EzI2Cs_ALT_ADDR_BIT:                        equ  0x80 ; Alternate Address bit
EzI2Cs_RW_FLAG:                             equ  0x01 ; Read/Write flag      
EzI2Cs_RD_FLAG:                             equ  0x01 ; Read/Write flag      
EzI2Cs_WR_FLAG:                             equ  0x00 ; Read/Write flag      

EzI2Cs_CFG_REG: equ d6h                 ; I2C Configuration Register
EzI2Cs_SCR_REG: equ d7h                 ; I2C Enable Master/Slave Block Operation
EzI2Cs_DR_REG:  equ d8h                 ; I2C Status and Control Register
EzI2Cs_MSCR_REG:    equ d9h             ; I2C Master Status and Control


;; Bit definitions for EzI2Cs_bState
EzI2Cs_ACTIVITY_MASK:      equ  0xB0      ; Activity Mask
EzI2Cs_ANY_ACTIVITY:       equ  0x80      ; Any I2C bus activity.
EzI2Cs_READ_ACTIVITY:      equ  0x20      ; I2C read activity at primary address.
EzI2Cs_WRITE_ACTIVITY:     equ  0x10      ; I2C write activity at primary address.

;--------------------------------------------------
;   EzI2Cs API Constants
;--------------------------------------------------

EzI2Cs_INT_REG:                            equ 0x0de
EzI2Cs_INT_MASK:                           equ 0x01


;I2C_(status and control) reg write macro
;----------------------------------------------------
;  I2C_SCR and I2C_MSCR reg write macro
;
;  Use the following macros to write to the I2C_SCR register
;  Usage:    SetI2C_SCR  WRITE_VALUE
;
;  where WRITE_VALUE is the data to be writen
;
;----------------------------------------------------


; Write to the  EzI2Cs_SCR register
    macro SetEzI2Cs_SCR
IF (EzI2Cs_SYNC_FIX)
        or    F, FLAG_XIO_MASK            ; set bank1
        push  X
        mov   X, A                        ; if data for I2C_SCR was in A save it in X
        mov   A, reg[OSC_CR0]             ;
        push  A
        and   A, ~0x07                          ; Mask off CPU speed
        or    A, 0x01                           ; Set CPU to 6 MHz
        mov   reg[OSC_CR0], A                   ; 
        and   F, ~FLAG_XIO_MASK                 ; set bank0
        mov   A, X                              ; if the operation uses data in A get it out of X
        mov   reg[EzI2Cs_SCR_REG], @0 ; write data to reg[I2C_SCR]
        or    F, FLAG_XIO_MASK                  ; set bank1
        pop   A                                 ; restore original clock speed
        mov   reg[OSC_CR0], A
        and   F, ~FLAG_XIO_MASK                 ; set bank0
        mov   A, X                              ; if A was data restore it from X now
        pop   X                                 ; restore original accumulator
ELSE
        mov   reg[EzI2Cs_SCR_REG], @0 ; write data to reg[I2C_SCR]
ENDIF
    endm

; end of file EzI2Cs.inc