ezi2csint.asm

cypress cy3721做的外部无线结点。感知温度后将温度值反给中心结点。

    ;            *** I2C Idle state ***
    ;
    ;   Sit idle until a start with address is issued.
    ;   Check to see if there is an address match
    ;     If address match, ACK the bus and determine next state
    ;     Else NAK the transfer and return to idle state.
    ;   Also check stop for condition.IF (EzI2Cs_ROM_ENABLE)  ;; Enable only if alternate ROM Address is Enabled
    ;
I2C_STATE_IDLE:                 ; Idle state

IF (EzI2Cs_DYNAMIC_ADDR)  ;; DYNAMIC ADDRESS
    mov  A,reg[EzI2Cs_DR_REG]                                        ; Get transmitted address
    and  A,EzI2Cs_ADDR_MASK                                          ; Mask off alt address bit and R/W bit
    cmp  A,[EzI2Cs_bAddr]                                            ; Check for proper Address
    jz   .CHK_ADDR_MODE 
    SetEzI2Cs_SCR ( EzI2Cs_SCR_NAK )                                 ; NAK Address 
    jmp  EzI2Cs_ISR_END                                              ; Not valid Address, leave

ELSE    ;; STATIC ADDRESS
    mov  A,reg[EzI2Cs_DR_REG]                                        ; Get transmitted address
    and  A,EzI2Cs_ADDR_MASK                                          ; Mask off alt address bit and R/W bit
    cmp  A,EzI2Cs_SLAVE_ADDR                                         ; Check for proper Address
    jz   .CHK_ADDR_MODE 
    SetEzI2Cs_SCR ( EzI2Cs_SCR_NAK )                                 ; NAK Address 
    jmp  EzI2Cs_ISR_END                                              ; Not valid Address, leave
ENDIF


.CHK_ADDR_MODE:   ; A proper address has been detected, now determine what mode, R/W alt_addr?? 
IF (EzI2Cs_ROM_ENABLE)  ;; Enable only if alternate ROM Address is Enabled
    tst  reg[EzI2Cs_DR_REG],EzI2Cs_ALT_ADDR_BIT                      ; Check for Alt address
    jnz  SERVICE_ROM_ADDR
ENDIF

.STANDARD_ADDR:   
    tst  reg[EzI2Cs_DR_REG],EzI2Cs_RD_FLAG                           ; Check for a Read operation
    jnz  .PREPARE_FOR_RAM_READ


    ; Prepare for RAM Write Address operation
    and  [EzI2Cs_bState],~STATE_MASK2                                ; Clear State bit.                       
    or   [EzI2Cs_bState],STATE_WR_RAM_ADDR                           ; Set state machine to do RAM Write
    SetEzI2Cs_SCR ( EzI2Cs_SCR_ACK )                                 ; ACK Address 
    jmp  EzI2Cs_ISR_END                                     ; Base address to RAM buffer.  

.PREPARE_FOR_RAM_READ:
    and  [EzI2Cs_bState],~STATE_MASK2                                ; Clear State bit.                       
    or   [EzI2Cs_bState],STATE_RD_RAM                                ; Set state machine to do RAM Read 
    mov  [EzI2Cs_bRAM_RWcntr],[EzI2Cs_bRAM_RWoffset]                 ; Reset address counter to start of Offset
    mov  A,[EzI2Cs_pRAM_Buf_Addr_LSB]                                ; Get base address
    add  A,[EzI2Cs_bRAM_RWcntr]                                      ; Set Offset and add to base address      
    mov  X,A                                                         ; Put offset in X
    mov  A,[X]                                                       ; Get first byte to transmit
    mov  reg[EzI2Cs_DR_REG],A                               ; Base address to RAM buffer.  
    inc  [EzI2Cs_bRAM_RWcntr]                                        ; Increment RAM buffer counter to next location.

                                                                     ; ACK command and transmit first byte.
    SetEzI2Cs_SCR (EzI2Cs_SCR_ACK|EzI2Cs_SCR_TRANSMIT)   
    jmp  EzI2Cs_ISR_END

    ;            *** I2C Read RAM state ***
    ;
I2C_STATE_RD_RAM:
    mov  A,[EzI2Cs_bRAM_Buf_Size]
    dec  A
    cmp  A,[EzI2Cs_bRAM_RWcntr]                                      ; Check to see if out of range.
    jc   .I2C_TRANSMIT_DATA  ; WARNING!! Bogas data will be transmitted if out of range.   

    mov  A,[EzI2Cs_pRAM_Buf_Addr_LSB]                                ; Get base address
    add  A,[EzI2Cs_bRAM_RWcntr]                                      ; Set Offset and add to base address      
    mov  X,A                                                         ; Put offset in X
    mov  A,[X]                                                       ; Get first byte to transmit
    mov  reg[EzI2Cs_DR_REG],A                                        ; Write data to transmit register
    inc  [EzI2Cs_bRAM_RWcntr]                                        ; Increment RAM buffer counter to next location.
    or   [EzI2Cs_bState],EzI2Cs_READ_ACTIVITY                        ; Set Read Activity flag


.I2C_TRANSMIT_DATA:     
    mov  reg[EzI2Cs_DR_REG],A                                        ; Write data to transmit register
    SetEzI2Cs_SCR ( EzI2Cs_SCR_TRANSMIT )                            ; ACK command and transmit first byte. 
    jmp  EzI2Cs_ISR_END


    ;            *** I2C Write RAM Address state ***
    ;
    ;  During this state, the RAM address offset is set.
I2C_STATE_WR_RAM_ADDR:              ; Wait for Address write state
    mov  A,reg[EzI2Cs_DR_REG]                                        ; Get transmitted Address offset
    cmp  A,[EzI2Cs_bRAM_Buf_Size]                                    ; Check if out of range.
    jnc  I2C_NAK_DATA                                                ; If out of range NAK address
    jz   I2C_NAK_DATA

    ; Address in range
    mov  [EzI2Cs_bRAM_RWcntr],A                                      ; Reset address counter with new value
    mov  [EzI2Cs_bRAM_RWoffset],A                                    ; Set offset with new value.
    and  [EzI2Cs_bState],~STATE_MASK2                                ; Clear State bit.                       
    or   [EzI2Cs_bState],STATE_WR_RAM                                ; Set state machine to do RAM Write
    jmp  I2C_ACK_DATA                         ; ACK the data


    ;            *** I2C Write RAM state
I2C_STATE_WR_RAM:  
   
    mov  A,[EzI2Cs_bRAM_Buf_WSize]                                   ; Get buffer size to make sure we
    jz   I2C_NAK_DATA                                                ; If RAM WSize is zero, do not allow write.
    dec  A                                                           ; are in a valid area.
    cmp  A,[EzI2Cs_bRAM_RWcntr]                                      ; Check to see if out of range.
    jc   I2C_NAK_DATA                                                ; If out of range NAK address

    mov  A,[EzI2Cs_pRAM_Buf_Addr_LSB]                                ; Get base address
    add  A,[EzI2Cs_bRAM_RWcntr]                                      ; Set Offset and add to base address      
    mov  X,A                                                         ; Put offset in X

    mov  A,reg[EzI2Cs_DR_REG]                                        ; Read data to be written
    mov  [X],A                                                       ; Store data in Buffer
    or   [EzI2Cs_bState],EzI2Cs_WRITE_ACTIVITY                       ; Set Write Activity flag
    inc  [EzI2Cs_bRAM_RWcntr]                                        ; Advance pointer to next location
    jmp  I2C_ACK_DATA                         ; ACK the data



IF (EzI2Cs_ROM_ENABLE)  ;; Enable only if alternate ROM Address is Enabled

SERVICE_ROM_ADDR:  ; At this time only ROM Read is supported.
    tst  reg[EzI2Cs_DR_REG],EzI2Cs_RD_FLAG                           ; Check for a Read operation
    jnz  PREPARE_FOR_ROM_READ

    and  [EzI2Cs_bState],~STATE_MASK2                                ; Clear State bit.                       
    or   [EzI2Cs_bState],STATE_WR_ROM_ADDR                           ; Set state machine to do ROM ADDR Write
    SetEzI2Cs_SCR ( EzI2Cs_SCR_ACK )                                 ; ACK Address 
    jmp  EzI2Cs_ISR_END                                    ; Base address to RAM buffer.  

    ; Prepare for Write ROM Address.              
I2C_STATE_WR_ROM_ADDR:
    mov  A,reg[EzI2Cs_DR_REG]                                        ; Get transmitted Address offset
    cmp  A,[EzI2Cs_bROM_Buf_Size]                                    ; Check if out of range.
    jnc  I2C_NAK_DATA                                                ; If out of range NAK address
    jz   I2C_NAK_DATA

    mov  [EzI2Cs_bROM_RWcntr],A                                      ; Reset address counter with new value
    mov  [EzI2Cs_bROM_RWoffset],A                                    ; Set offset with new value.
    and  [EzI2Cs_bState],~STATE_MASK2                                ; Clear State bit.                       
    or   [EzI2Cs_bState],STATE_WR_ROM                                ; Set state machine to do ROM Write
    jmp  I2C_ACK_DATA

I2C_STATE_WR_ROM:  // Flash command interpreter
   ;@PSoC_UserCode_ROM_WR@ (Do not change this line.)
   ;---------------------------------------------------
   ; Insert your custom code below this banner
   ;---------------------------------------------------
   ;   NOTE: interrupt service routines must preserve
   ;   the values of the A and X CPU registers.
    lcall EzI2Cs_Execute_CMD                                        ; Parameter byte found, execute command.
    cmp  A,0x00
    jz   I2C_NAK_DATA                                                ; Return zero, NAK the command
    jmp  I2C_ACK_DATA       
   ;---------------------------------------------------
   ; Insert your custom code above this banner
   ;---------------------------------------------------
   ;@PSoC_UserCode_END@ (Do not change this line.)

    jnc  I2C_NAK_DATA                                                ; Write to ROM not supported.

PREPARE_FOR_ROM_READ:
    and  [EzI2Cs_bState],~STATE_MASK2                                ; Clear State bit.                       
    or   [EzI2Cs_bState],STATE_RD_ROM                                ; Set state machine to do ROM Read 
    mov  [EzI2Cs_bROM_RWcntr],[EzI2Cs_bROM_RWoffset]                 ; Reset address counter to start of Offset
    mov  X,[EzI2Cs_pROM_Buf_Addr_MSB]                                ; Get MSB of ROM address in X
    mov  A,[EzI2Cs_pROM_Buf_Addr_LSB]                                ; Get LSB of ROM base address
    add  A,[EzI2Cs_bROM_RWcntr]                                      ; Set Offset and add to base address      
    jnc  .GET_ROM_VALUE
    inc  X    ; Inc the MSB
.GET_ROM_VALUE:
    swap A,X  ; Place MSB of ROM address in A, and LSB in X for ROMX
    romx      ; Get Rom value in A

    mov  reg[EzI2Cs_DR_REG],A                              ; Base address to RAM buffer.  
    inc  [EzI2Cs_bROM_RWcntr]                                        ; Increment RAM buffer counter to next location.

                                                                     ; ACK command and transmit first byte.
    SetEzI2Cs_SCR  (EzI2Cs_SCR_ACK|EzI2Cs_SCR_TRANSMIT)   
    jmp  EzI2Cs_ISR_END


I2C_STATE_RD_ROM:
    mov  A,[EzI2Cs_bROM_Buf_Size]
    dec  A
    cmp  A,[EzI2Cs_bROM_RWcntr]                                      ; Check to see if out of range.
    jc   .I2C_TRANSMIT_ROM_DATA  ; WARNING!! Bogas data will be transmitted if out of range.   

    mov  X,[EzI2Cs_pROM_Buf_Addr_MSB]                                ; Get MSB of ROM address in X
    mov  A,[EzI2Cs_pROM_Buf_Addr_LSB]                                ; Get LSB of ROM base address
    add  A,[EzI2Cs_bROM_RWcntr]                                      ; Set Offset and add to base address      
    jnc  .GET_ROM_VALUE
    inc  X    ; Inc the MSB
.GET_ROM_VALUE:
    swap A,X  ; Place MSB of ROM address in A, and LSB in X for ROMX
    romx      ; Get Rom value in A
    mov  reg[EzI2Cs_DR_REG],A                              ; Base address to RAM buffer.  
    inc  [EzI2Cs_bROM_RWcntr]                                        ; Increment RAM buffer counter to next location.

.I2C_TRANSMIT_ROM_DATA:     
    mov  reg[EzI2Cs_DR_REG],A                                        ; Write data to transmit register
    SetEzI2Cs_SCR  (EzI2Cs_SCR_TRANSMIT)                             ; ACK command and transmit first byte. 
    jmp  EzI2Cs_ISR_END

ENDIF

;; Generic handlers

I2C_ACK_DATA:
    SetEzI2Cs_SCR ( EzI2Cs_SCR_ACK )                                 ; ACK Data
    jmp  EzI2Cs_ISR_END

I2C_NAK_DATA:   ;; NAK data and return  !!WARNING, NOT SURE IF THIS WILL WORK
    SetEzI2Cs_SCR ( EzI2Cs_SCR_NAK )                                 ;  NAK Data
    jmp  EzI2Cs_ISR_END

I2C_STATE_RESET:
    and  [EzI2Cs_bState],~STATE_MASK2                                ; Clear State bit.                       
    or   [EzI2Cs_bState], STATE_IDLE    ; Reset State
    ; Reset pointer buffers as well


EzI2Cs_ISR_END:

; This conditional code is only used when using the large memory model.
IF (SYSTEM_LARGE_MEMORY_MODEL)
   REG_RESTORE CUR_PP           ; Restore Current Page Pointer
   REG_RESTORE IDX_PP           ; Restore Index Page Pointer
ENDIF
    pop  X
    pop  A

    reti





; end of file EzI2CsINT.asm