📄 systemtimerint.lst
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499 ; Global Interrupt Enable/Disable
500 ;----------------------------------------------------
501 macro M8C_EnableGInt
502 or F, FLAG_GLOBAL_IE
503 1C5C endm
504
505 macro M8C_DisableGInt
506 and F, ~FLAG_GLOBAL_IE
507 1C5C endm
508
509 ;----------------------------------------------------
510 ; Enable/Disable Interrupt Mask
511 ;
512 ; Use the following macros to enable/disable
513 ; bits in the Interrupt mask registers,
514 ; INT_MSK0, INT_MSK1 or INT_MSK3.
515 ;
516 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
517 ; M8C_EnableIntMask INT_MSKN, MASK
518 ;
519 ; where INT_MSKN is INT_MSK0, INT_MSK1 or INT_MSK3
520 ; and MASK is the bit set to enable or disable
521 ;----------------------------------------------------
522 ; Disable Interrupt Bit Mask(s)
523 macro M8C_DisableIntMask
524 and reg[@0], ~@1 ; disable specified interrupt enable bit
525 1C5C endm
526
527 ; Enable Interrupt Bit Mask(s)
528 macro M8C_EnableIntMask
529 or reg[@0], @1 ; enable specified interrupt enable bit
530 1C5C endm
531
532 ;----------------------------------------------------
533 ; Clear Posted Interrupt Flag Mask
534 ;
535 ; Use the following macros to clear the
536 ; bits in the Interrupt Clear registers,
537 ; INT_CLR0, INT_CLR1 or INT_CLR3.
538 ; Usage: M8C_ClearIntFlag INT_CLRN, MASK
539 ;
540 ; where INT_MSKN is INT_CLR0, INT_CLR1 or INT_CLR3
541 ; and MASK is the bit set to enable or disable
542 ;----------------------------------------------------
543 macro M8C_ClearIntFlag
544 mov reg[@0], ~@1 ; clear specified interrupt enable bit
545 1C5C endm
546
547 ;----------------------------------------------------
548 ; Power-On Reset & WatchDog Timer Functions
549 ;----------------------------------------------------
550 macro M8C_EnableWatchDog
551 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
552 1C5C endm
553
554 macro M8C_ClearWDT
555 mov reg[RES_WDT], 00h
556 1C5C endm
557
558 macro M8C_ClearWDTAndSleep
559 mov reg[RES_WDT], 38h
560 1C5C endm
561
562 ;----------------------------------------------------
563 ; Sleep, CPU Stop & Software Reset
564 ;----------------------------------------------------
565 macro M8C_Sleep
566 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
567 ; The next instruction to be executed depends on the state of the
568 ; various interrupt enable bits. If some interrupts are enabled
569 ; and the global interrupts are disabled, the next instruction will
570 ; be the one that follows the invocation of this macro. If global
571 ; interrupts are also enabled then the next instruction will be
572 ; from the interrupt vector table. If no interrupts are enabled
573 ; then the CPU sleeps forever.
574 1C5C endm
575
576 macro M8C_Stop
577 ; In general, you probably don't want to do this, but here's how:
578 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
579 ; Next instruction to be executed is located in the interrupt
580 ; vector table entry for Power-On Reset.
581 1C5C endm
582
583 macro M8C_Reset
584 ; Restore CPU to the power-on reset state.
585 mov A, 0
586 SSC
587 ; Next non-supervisor instruction will be at interrupt vector 0.
588 1C5C endm
589
590 ;----------------------------------------------------
591 ; ImageCraft Code Compressor Actions
592 ;----------------------------------------------------
593 ; Suspend Code Compressor
594 ; Must not span a RET or RETI instruction
595 ; without resuming code compression
596 macro Suspend_CodeCompressor
597 or F, 0
598 1C5C endm
599
600 ; Resume Code Compression
601 macro Resume_CodeCompressor
602 add SP, 0
603 1C5C endm
1 ;;*****************************************************************************
2 ;;*****************************************************************************
3 ;; FILENAME: SystemTimer.inc
4 ;; Version: 1.0, Updated on 2008/10/2 at 14:39:26
5 ;; Generated by PSoC Designer ???
6 ;;
7 ;; DESCRIPTION: Assembler declarations for the SleepTimer user module interface
8 ;; for the 22/24/27/29/42xxx PSoC family of devices
9 ;;-----------------------------------------------------------------------------
10 ;; Copyright (c) Cypress MicroSystems 2000-2006. All Rights Reserved.
11 ;;*****************************************************************************
12 ;;*****************************************************************************
13
14 include "m8c.inc"
15
16
17 ;--------------------------------------------------
18 ; Constants for SystemTimer API's.
19 ;--------------------------------------------------
20
21 00E0 SystemTimer_INT_REG: equ 0x0e0
22 0040 SystemTimer_INT_MASK: equ 0x40
23
24 0002 SystemTimer_TICK_CNTR_SIZE: equ 2h
25 0001 SystemTimer_PSOC_TYPE: equ 1
26
27 IF (SystemTimer_PSOC_TYPE) ; 22/24/27/29xxx Family
28
29 ; Frequency of sleep timer interrupts
30 0018 SystemTimer_1_HZ: equ 0x18
31 0010 SystemTimer_8_HZ: equ 0x10
32 0008 SystemTimer_64_HZ: equ 0x08
33 0000 SystemTimer_512_HZ: equ 0x00
34 0018 SystemTimer_CLOCK_MASK: equ 0x18
35 ELSE ; 42020 Family
36
37 ; Frequency of sleep timer interrupts
38 SystemTimer_1_HZ: equ 0x03
39 SystemTimer_8_HZ: equ 0x02
40 SystemTimer_64_HZ: equ 0x01
41 SystemTimer_512_HZ: equ 0x00
42 SystemTimer_CLOCK_MASK: equ 0x03
43 ENDIF
44
45
46 0001 SystemTimer_FORCE_RELOAD: equ 0x01
47 0000 SystemTimer_WAIT_RELOAD: equ 0x00
1 ;;*****************************************************************************
2 ;;*****************************************************************************
3 ;;
4 ;; FILENAME: Memory.inc
5 ;;
6 ;; DESCRIPTION: Memory Model and Stack Parameter Definitions for
7 ;; 21x3x PSoC devices.
8 ;;
9 ;; LAST MODIFIED: August 17, 2004
10 ;;
11 ;;-----------------------------------------------------------------------------
12 ;; Copyright (c) Cypress MicroSystems 2004. All Rights Reserved.
13 ;;*****************************************************************************
14 ;;*****************************************************************************
15 ;
16 ;
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